AT32UC3C0256C Atmel Corporation, AT32UC3C0256C Datasheet - Page 163
AT32UC3C0256C
Manufacturer Part Number
AT32UC3C0256C
Description
Manufacturer
Atmel Corporation
Datasheets
1.AT32UC3A0128.pdf
(377 pages)
2.AT32UC3A0128.pdf
(159 pages)
3.AT32UC3C0128C.pdf
(1313 pages)
4.AT32UC3C0128C.pdf
(108 pages)
Specifications of AT32UC3C0256C
Flash (kbytes)
256 Kbytes
Pin Count
144
Max. Operating Frequency
66 MHz
Cpu
32-bit AVR
Hardware Qtouch Acquisition
No
Max I/o Pins
123
Ext Interrupts
144
Usb Transceiver
1
Quadrature Decoder Channels
2
Usb Speed
Full Speed
Usb Interface
Device + OTG
Spi
7
Twi (i2c)
3
Uart
5
Can
2
Lin
5
Ssc
1
Ethernet
1
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
16
Adc Resolution (bits)
12
Adc Speed (ksps)
2000
Analog Comparators
4
Resistive Touch Screen
No
Dac Channels
4
Dac Resolution (bits)
12
Temp. Sensor
No
Crypto Engine
No
Sram (kbytes)
68
Self Program Memory
YES
External Bus Interface
1
Dram Memory
sdram
Nand Interface
No
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
3.0 to 3.6 or 4.5 to 5.5
Operating Voltage (vcc)
3.0 to 3.6 or 4.5 to 5.5
Fpu
Yes
Mpu / Mmu
Yes / No
Timers
6
Output Compare Channels
22
Input Capture Channels
12
Pwm Channels
20
32khz Rtc
Yes
Calibrated Rc Oscillator
Yes
Available stocks
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- AT32UC3A0128 PDF datasheet
- AT32UC3A0128 PDF datasheet #2
- AT32UC3C0128C PDF datasheet #3
- AT32UC3C0128C PDF datasheet #4
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10.5.1.3
10.5.1.4
10.5.1.5
32117C–AVR-08/11
Configuring the WDT
Enabling the WDT
Clearing the WDT Counter
To change the clock for the WDT the following steps need to be taken. Note that the WDT
should always be disabled before changing the CLK_CNT source:
1. Write a zero to the Clock Enable (CEN) bit in the CTRL Register, leaving the other bits as they
are in the CTRL Register. This will stop CLK_CNT.
2. Read back the CTRL Register until the CEN bit reads zero. The clock has now been stopped.
3. Modify the Clock Source Select (CSSEL) bit in the CTRL Register with your new clock selec-
tion and write it to the CTRL Register.
4. Write a one to the CEN bit, leaving the other bits as they are in the CTRL Register. This will
enable the clock.
5. Read back the CTRL Register until the CEN bit reads one. The clock has now been enabled.
If the MODE bit in the CTRL Register is zero, the WDT is in basic mode. The Time Out Prescale
Select (PSEL) field in the CTRL Register selects the WDT timeout period:
To enable the WDT write a one to the Enable (EN) bit in the CTRL Register. Due to internal syn-
chronization, it will take some time for the CTRL.EN bit to read back as one.
The WDT counter is cleared by writing a one to the Watchdog Clear (WDTCLR) bit in the Clear
(CLR) Register, at any correct write to the CTRL Register, or when the counter reaches T
and the chip is reset. In basic mode the CLR.WDTCLR can be written at any time when the WDT
Counter Cleared (CLEARED) bit in the Status Register (SR) is one. Due to internal synchroniza-
tion, clearing the WDT counter takes some time. The SR.CLEARED bit is cleared when writing
to CLR.WDTCLR bit and set when the clearing is done. Any write to the CLR.WDTCLR bit while
SR.CLEARED is zero will not clear the counter.
Writing to the CLR.WDTCLR bit has to be done in a particular sequence to be valid. The CLR
Register must be written twice, first with the KEY field set to 0x55 and WDTCLR set to one, then
a second write with the KEY set to 0xAA without changing the WDTCLR bit. Writing to the CLR
Register without the correct sequence has no effect.
If the WDT counter is periodically cleared within T
ure 10-2 on page
T
timeout
= T
psel
164.
= 2
(PSEL+1)
/ f
clk_cnt
psel
no watchdog reset will be issued, see
AT32UC3C
timeout
Fig-
163
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