AT32UC3C0256C Atmel Corporation, AT32UC3C0256C Datasheet - Page 517
AT32UC3C0256C
Manufacturer Part Number
AT32UC3C0256C
Description
Manufacturer
Atmel Corporation
Datasheets
1.AT32UC3A0128.pdf
(377 pages)
2.AT32UC3A0128.pdf
(159 pages)
3.AT32UC3C0128C.pdf
(1313 pages)
4.AT32UC3C0128C.pdf
(108 pages)
Specifications of AT32UC3C0256C
Flash (kbytes)
256 Kbytes
Pin Count
144
Max. Operating Frequency
66 MHz
Cpu
32-bit AVR
Hardware Qtouch Acquisition
No
Max I/o Pins
123
Ext Interrupts
144
Usb Transceiver
1
Quadrature Decoder Channels
2
Usb Speed
Full Speed
Usb Interface
Device + OTG
Spi
7
Twi (i2c)
3
Uart
5
Can
2
Lin
5
Ssc
1
Ethernet
1
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
16
Adc Resolution (bits)
12
Adc Speed (ksps)
2000
Analog Comparators
4
Resistive Touch Screen
No
Dac Channels
4
Dac Resolution (bits)
12
Temp. Sensor
No
Crypto Engine
No
Sram (kbytes)
68
Self Program Memory
YES
External Bus Interface
1
Dram Memory
sdram
Nand Interface
No
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
3.0 to 3.6 or 4.5 to 5.5
Operating Voltage (vcc)
3.0 to 3.6 or 4.5 to 5.5
Fpu
Yes
Mpu / Mmu
Yes / No
Timers
6
Output Compare Channels
22
Input Capture Channels
12
Pwm Channels
20
32khz Rtc
Yes
Calibrated Rc Oscillator
Yes
Available stocks
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- AT32UC3A0128 PDF datasheet
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- AT32UC3C0128C PDF datasheet #3
- AT32UC3C0128C PDF datasheet #4
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24.7.8
Name:
Access Type:
Offset:
Reset Value:
• PTZ: Pause Time Zero
• PFR: Pause Frame Received
• HRESP: Hresp Not OK
• ROVR: Receive Overrun
• TCOMP: Transmit Complete
• TXERR: Transmit Error
32117C–AVR-08/11
TCOMP
31
23
15
7
-
-
-
This bit is set when the pause time register (PTR) decrements to zero.
This bit is cleared after read.
0: PTR > 0.
1: PTR = 0.
This bit is cleared after read.
0: No valid pause frame received.
1: Valid pause frame received.
This bit is set when the DMA interface detects a bus error.
This bit is cleared after read.
0: HRESP is OK.
1: HRESP is not OK.
This bit is set when the receive overrun status bit is set (RSR.OVR).
This bit is cleared after read.
0: RSR.OVR is not set.
1: RSR.OVR has been set.
This bit is set when a frame has been transmitted.
This bit is cleared after read.
0: Transmit is not completed.
1: Transmit is completed.
This bit is set when transmit buffers exhausted in mid-frame.
Interrupt Status Register
TXERR
30
22
14
6
-
-
-
ISR
Read/Write
0x24
0x00000000
RLE
PTZ
29
21
13
5
-
-
TUND
PFR
28
20
12
4
-
-
HRESP
TXUBR
27
19
11
3
-
-
RXUBR
ROVR
26
18
10
2
-
-
RCOMP
25
17
9
1
-
-
-
AT32UC3C
MFD
24
16
8
0
-
-
-
517
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