AT32UC3C0256C Atmel Corporation, AT32UC3C0256C Datasheet - Page 722
AT32UC3C0256C
Manufacturer Part Number
AT32UC3C0256C
Description
Manufacturer
Atmel Corporation
Datasheets
1.AT32UC3A0128.pdf
(377 pages)
2.AT32UC3A0128.pdf
(159 pages)
3.AT32UC3C0128C.pdf
(1313 pages)
4.AT32UC3C0128C.pdf
(108 pages)
Specifications of AT32UC3C0256C
Flash (kbytes)
256 Kbytes
Pin Count
144
Max. Operating Frequency
66 MHz
Cpu
32-bit AVR
Hardware Qtouch Acquisition
No
Max I/o Pins
123
Ext Interrupts
144
Usb Transceiver
1
Quadrature Decoder Channels
2
Usb Speed
Full Speed
Usb Interface
Device + OTG
Spi
7
Twi (i2c)
3
Uart
5
Can
2
Lin
5
Ssc
1
Ethernet
1
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
16
Adc Resolution (bits)
12
Adc Speed (ksps)
2000
Analog Comparators
4
Resistive Touch Screen
No
Dac Channels
4
Dac Resolution (bits)
12
Temp. Sensor
No
Crypto Engine
No
Sram (kbytes)
68
Self Program Memory
YES
External Bus Interface
1
Dram Memory
sdram
Nand Interface
No
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
3.0 to 3.6 or 4.5 to 5.5
Operating Voltage (vcc)
3.0 to 3.6 or 4.5 to 5.5
Fpu
Yes
Mpu / Mmu
Yes / No
Timers
6
Output Compare Channels
22
Input Capture Channels
12
Pwm Channels
20
32khz Rtc
Yes
Calibrated Rc Oscillator
Yes
Available stocks
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Manufacturer
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Price
- AT32UC3A0128 PDF datasheet
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- AT32UC3C0128C PDF datasheet #3
- AT32UC3C0128C PDF datasheet #4
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27.9.8
Name:
Access Type:
Offset:
Reset Value:
• MENB: Master Interface Enable
• STOP: Stop Request Accepted
• PECERR: PEC Error
• TOUT: Timeout
• SMBALERT: SMBus Alert
• ARBLST: Arbitration Lost
• DNAK: NAK in Data Phase Received
• ANAK: NAK in Address Phase Received
• BUSFREE: Two-wire Bus is Free
32117C–AVR-08/11
31
23
15
7
-
-
-
-
0: Master interface is disabled.
1: Master interface is enabled.
This bit is one when STOP request caused by setting CR STOP has been accepted, and transfer has stopped.
This bit is cleared by writing 1 to the corresponding bit in the Status Clear Register (SCR).
This bit is one when a SMBus PEC error occurred.
This bit is cleared by writing 1 to the corresponding bit in the Status Clear Register (SCR).
This bit is one when a SMBus timeout occurred.
This bit is cleared by writing 1 to the corresponding bit in the Status Clear Register (SCR).
This bit is one when an SMBus Alert was received.
This bit is cleared by writing 1 to the corresponding bit in the Status Clear Register (SCR).
This bit is one when the actual state of the SDA line did not correspond to the data driven onto it, indicating a higher-priority
transmission in progress by a different master.
This bit is cleared by writing 1 to the corresponding bit in the Status Clear Register (SCR).
This bit is one when no ACK was received form slave during data transmission.
This bit is cleared by writing 1 to the corresponding bit in the Status Clear Register (SCR).
This bit is one when no ACK was received from slave during address phase
This bit is cleared by writing 1 to the corresponding bit in the Status Clear Register (SCR).
This bit is one when activity has completed on the two-wire bus.
Status Register
STOP
30
22
14
6
-
-
-
SR
Read-only
0x1C
0x00000002
BUSFREE
PECERR
29
21
13
5
-
-
TOUT
IDLE
28
20
12
4
-
-
SMBALERT
CCOMP
27
19
11
3
-
-
ARBLST
CRDY
26
18
10
2
-
-
TXRDY
DNAK
25
17
9
1
-
-
AT32UC3C
RXRDY
MENB
ANAK
24
16
8
0
-
722
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