AT32UC3C0256C Atmel Corporation, AT32UC3C0256C Datasheet - Page 1101
AT32UC3C0256C
Manufacturer Part Number
AT32UC3C0256C
Description
Manufacturer
Atmel Corporation
Datasheets
1.AT32UC3A0128.pdf
(377 pages)
2.AT32UC3A0128.pdf
(159 pages)
3.AT32UC3C0128C.pdf
(1313 pages)
4.AT32UC3C0128C.pdf
(108 pages)
Specifications of AT32UC3C0256C
Flash (kbytes)
256 Kbytes
Pin Count
144
Max. Operating Frequency
66 MHz
Cpu
32-bit AVR
Hardware Qtouch Acquisition
No
Max I/o Pins
123
Ext Interrupts
144
Usb Transceiver
1
Quadrature Decoder Channels
2
Usb Speed
Full Speed
Usb Interface
Device + OTG
Spi
7
Twi (i2c)
3
Uart
5
Can
2
Lin
5
Ssc
1
Ethernet
1
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
16
Adc Resolution (bits)
12
Adc Speed (ksps)
2000
Analog Comparators
4
Resistive Touch Screen
No
Dac Channels
4
Dac Resolution (bits)
12
Temp. Sensor
No
Crypto Engine
No
Sram (kbytes)
68
Self Program Memory
YES
External Bus Interface
1
Dram Memory
sdram
Nand Interface
No
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
3.0 to 3.6 or 4.5 to 5.5
Operating Voltage (vcc)
3.0 to 3.6 or 4.5 to 5.5
Fpu
Yes
Mpu / Mmu
Yes / No
Timers
6
Output Compare Channels
22
Input Capture Channels
12
Pwm Channels
20
32khz Rtc
Yes
Calibrated Rc Oscillator
Yes
Available stocks
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- AT32UC3A0128 PDF datasheet
- AT32UC3A0128 PDF datasheet #2
- AT32UC3C0128C PDF datasheet #3
- AT32UC3C0128C PDF datasheet #4
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36. ADC Interface (ADCIFA)
36.1
32117C–AVR-08/11
Features
Rev. 1.1.0.2
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8/10/12-bit ADC core with built-in dual sample and hold (S/H)
16 channels
Up to 1.5 mega-samples per second conversion rate for 12 bits resolution
Up to 2 mega-samples per second conversion for lower resolution
Multiple reference sources
Direct measures or sampled with sample-and-hold
Sample-and-hold (S/H) acquisition time window has separate prescale control (gain: 1, 2, 4, 8, 16,
32, 64).
Sequencer can be operated as two independent 8-state sequencers operating on its own S/H
(dual sequencer mode) or as one large 16-state sequencer (single sequencer mode)
16 result registers
Source selection for the start-of-conversion (SOC)
Two sequencer modes:
Flexible interrupt control allows interrupt request on every end-of-sequence or on every single
conversion.
Windowing mechanism, with selectable channel
Free running mode
2 PDCA channels (one per sequencer)
Power reduction modes
Programmable ADC timings
– Conversion time near to 5.3µs (12 bits resolution at 1.5 Msps)
– Conversion time near to 3.5µs (10 bits resolution at 2 Msps)
– Conversion time near to 3µs (8 bits resolution at 2 Msps)
– 1V internal voltage reference
– 0.6 * VDDANA internal
– Two external reference voltage
– Software
– Embedded timer
– Peripheral Event Controller
– Continuous
– Run the whole sequence on a start-of-conversion
– Run a single conversion on a start-of-conversion
AT32UC3C
1101
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