AT32UC3B064 Atmel Corporation, AT32UC3B064 Datasheet - Page 422
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AT32UC3B064
Manufacturer Part Number
AT32UC3B064
Description
Manufacturer
Atmel Corporation
Datasheets
1.AT32UC3A0128.pdf
(377 pages)
2.AT32UC3A0128.pdf
(33 pages)
3.AT32UC3A0128.pdf
(159 pages)
4.AT32UC3B0128.pdf
(684 pages)
5.AT32UC3B0128.pdf
(107 pages)
Specifications of AT32UC3B064
Flash (kbytes)
64 Kbytes
Pin Count
64
Max. Operating Frequency
60 MHz
Cpu
32-bit AVR
# Of Touch Channels
32
Hardware Qtouch Acquisition
No
Max I/o Pins
44
Ext Interrupts
44
Usb Transceiver
1
Usb Speed
Full Speed
Usb Interface
Device + OTG
Spi
4
Twi (i2c)
1
Uart
3
Ssc
1
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
8
Adc Resolution (bits)
10
Adc Speed (ksps)
384
Resistive Touch Screen
No
Temp. Sensor
No
Crypto Engine
No
Sram (kbytes)
16
Self Program Memory
YES
Dram Memory
No
Nand Interface
No
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
3.0-3.6 or (1.65-1.95+3.0-3.6)
Operating Voltage (vcc)
3.0-3.6 or (1.65-1.95+3.0-3.6)
Fpu
No
Mpu / Mmu
Yes / No
Timers
10
Output Compare Channels
16
Input Capture Channels
6
Pwm Channels
13
32khz Rtc
Yes
Calibrated Rc Oscillator
Yes
Available stocks
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- AT32UC3A0128 PDF datasheet
- AT32UC3A0128 PDF datasheet #2
- AT32UC3A0128 PDF datasheet #3
- AT32UC3B0128 PDF datasheet #4
- AT32UC3B0128 PDF datasheet #5
- Current page: 422 of 684
- Download datasheet (11Mb)
22.8.2.8
Register Name:
Access Type:
Offset:
Reset Value:
• EPRSTn: Endpoint n Reset
• EPENn: Endpoint n Enable
32059L–AVR32–01/2012
31
23
15
7
-
-
-
-
Writing a one to this bit will reset the endpoint n FIFO prior to any other operation, upon hardware reset or when a USB bus
reset has been received. This resets the endpoint n registers (UECFGn, UESTAn, UECONn) but not the endpoint configuration
(ALLOC, EPBK, EPSIZE, EPDIR, EPTYPE).
All the endpoint mechanism (FIFO counter, reception, transmission, etc.) is reset apart from the Data Toggle Sequence field
(DTSEQ) which can be cleared by setting the RSTDT bit (by writing a one to the RSTDTS bit).
The endpoint configuration remains active and the endpoint is still enabled.
Writing a zero to this bit will complete the reset operation and start using the FIFO.
This bit is cleared upon receiving a USB reset.
1: The endpoint n is enabled.
0: The endpoint n is disabled, what forces the endpoint n state to inactive (no answer to USB requests) and resets the endpoint
n registers (UECFGn, UESTAn, UECONn) but not the endpoint configuration (ALLOC, EPBK, EPSIZE, EPDIR, EPTYPE).
Endpoint Enable/Reset Register
EPRST6
EPEN6
30
22
14
6
-
-
UERST
Read/Write
0x001C
0x00000000
EPRST5
EPEN5
29
21
13
5
-
-
EPRST4
EPEN4
28
20
12
4
-
-
EPRST3
EPEN3
27
19
11
3
-
-
EPRST2
EPEN2
26
18
10
2
-
-
EPRST1
EPEN1
25
17
9
1
-
-
EPRST0
EPEN0
24
16
8
0
-
-
422
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