AT32UC3B064 Atmel Corporation, AT32UC3B064 Datasheet - Page 300
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AT32UC3B064
Manufacturer Part Number
AT32UC3B064
Description
Manufacturer
Atmel Corporation
Datasheets
1.AT32UC3A0128.pdf
(377 pages)
2.AT32UC3A0128.pdf
(33 pages)
3.AT32UC3A0128.pdf
(159 pages)
4.AT32UC3B0128.pdf
(684 pages)
5.AT32UC3B0128.pdf
(107 pages)
Specifications of AT32UC3B064
Flash (kbytes)
64 Kbytes
Pin Count
64
Max. Operating Frequency
60 MHz
Cpu
32-bit AVR
# Of Touch Channels
32
Hardware Qtouch Acquisition
No
Max I/o Pins
44
Ext Interrupts
44
Usb Transceiver
1
Usb Speed
Full Speed
Usb Interface
Device + OTG
Spi
4
Twi (i2c)
1
Uart
3
Ssc
1
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
8
Adc Resolution (bits)
10
Adc Speed (ksps)
384
Resistive Touch Screen
No
Temp. Sensor
No
Crypto Engine
No
Sram (kbytes)
16
Self Program Memory
YES
Dram Memory
No
Nand Interface
No
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
3.0-3.6 or (1.65-1.95+3.0-3.6)
Operating Voltage (vcc)
3.0-3.6 or (1.65-1.95+3.0-3.6)
Fpu
No
Mpu / Mmu
Yes / No
Timers
10
Output Compare Channels
16
Input Capture Channels
6
Pwm Channels
13
32khz Rtc
Yes
Calibrated Rc Oscillator
Yes
Available stocks
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Part Number
Manufacturer
Quantity
Price
- AT32UC3A0128 PDF datasheet
- AT32UC3A0128 PDF datasheet #2
- AT32UC3A0128 PDF datasheet #3
- AT32UC3B0128 PDF datasheet #4
- AT32UC3B0128 PDF datasheet #5
- Current page: 300 of 684
- Download datasheet (11Mb)
21.6
21.6.1
21.6.2
Figure 21-2. Baud Rate Generator
21.6.2.1
32059L–AVR32–01/2012
Functional Description
Selecting Mode
Baud Rate Generator
CLK_USART/DIV
CLK
CLK_USART
Baud Rate in Asynchronous Mode
Reserved
USCLKS
The USART can operate in several modes. The operating mode is selected by writing to the
Mode field in the
mode is selected by writing to the Synchronous Mode Select bit in MR (MR.SYNC).
The baud rate generator provides the bit period clock named the Baud Rate Clock to both
receiver and transmitter. It is based on a 16-bit divider, which is specified in the Clock Divider
field in the Baud Rate Generator Register (BRGR.CD). A non-zero value enables the generator,
and if CD is one, the divider is bypassed and inactive. The Clock Selection field in the Mode
Register (MR.USCLKS) selects clock source between:
If the external CLK clock is selected, the duration of the low and high levels of the signal pro-
vided on the CLK pin must be at least 4.5 times longer than those provided by CLK_USART.
If the USART is configured to operate in an asynchronous mode, the selected clock is divided by
the CD value before it is provided to the receiver as a sampling clock. Depending on the Over-
sampling Mode bit (MR.OVER) value, the clock is then divided by either 8 (OVER=1), or 16
(OVER=0). The baud rate is calculated with the following formula:
This gives a maximum baud rate of CLK_USART divided by 8, assuming that CLK_USART is
the fastest clock possible, and that OVER is one.
0
1
3
2
• CLK_USART (internal clock, refer to Power Manager chapter for details)
• CLK_USART/DIV (a divided CLK_USART, refer to Module Configuration section)
• CLK (external clock, available on the CLK pin)
BaudRate
16-bit Counter
=
“Mode Register”
CD
----------------------------------------------- -
(
8 2 OVER
SelectedClock
(
–
USCLKS= 3
0
SYNC
)CD
)
(MR.MODE). In addition, Synchronous or Asynchronous
CD
>1
0
1
0
1
OVER
Sampling
Divider
FIDI
0
1
SYNC
CLK
BaudRate
Sampling
Clock
Clock
300
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