AT32UC3B064 Atmel Corporation, AT32UC3B064 Datasheet - Page 307
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AT32UC3B064
Manufacturer Part Number
AT32UC3B064
Description
Manufacturer
Atmel Corporation
Datasheets
1.AT32UC3A0128.pdf
(377 pages)
2.AT32UC3A0128.pdf
(33 pages)
3.AT32UC3A0128.pdf
(159 pages)
4.AT32UC3B0128.pdf
(684 pages)
5.AT32UC3B0128.pdf
(107 pages)
Specifications of AT32UC3B064
Flash (kbytes)
64 Kbytes
Pin Count
64
Max. Operating Frequency
60 MHz
Cpu
32-bit AVR
# Of Touch Channels
32
Hardware Qtouch Acquisition
No
Max I/o Pins
44
Ext Interrupts
44
Usb Transceiver
1
Usb Speed
Full Speed
Usb Interface
Device + OTG
Spi
4
Twi (i2c)
1
Uart
3
Ssc
1
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
8
Adc Resolution (bits)
10
Adc Speed (ksps)
384
Resistive Touch Screen
No
Temp. Sensor
No
Crypto Engine
No
Sram (kbytes)
16
Self Program Memory
YES
Dram Memory
No
Nand Interface
No
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
3.0-3.6 or (1.65-1.95+3.0-3.6)
Operating Voltage (vcc)
3.0-3.6 or (1.65-1.95+3.0-3.6)
Fpu
No
Mpu / Mmu
Yes / No
Timers
10
Output Compare Channels
16
Input Capture Channels
6
Pwm Channels
13
32khz Rtc
Yes
Calibrated Rc Oscillator
Yes
Available stocks
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Part Number
Manufacturer
Quantity
Price
- AT32UC3A0128 PDF datasheet
- AT32UC3A0128 PDF datasheet #2
- AT32UC3A0128 PDF datasheet #3
- AT32UC3B0128 PDF datasheet #4
- AT32UC3B0128 PDF datasheet #5
- Current page: 307 of 684
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21.6.4.3
32059L–AVR32–01/2012
Asynchronous Receiver
Figure 21-9. Start Frame Delimiter
Manchester Drift Compensation
The Drift compensation bit (MAN.DRIFT) enables a hardware drift compensation and recovery
system that allows for sub-optimal clock drifts without further user intervention. Drift compensa-
tion is only available in 16x oversampling mode. If the RXD event is one 16
the expected edge, it is considered as normal jitter and no corrective action will be taken. If the
event is two to four 16
to three 16
Figure 21-10. Bit Resynchronization
If the USART is configured in an asynchronous operating mode (MR.SYNC = 0), the receiver will
oversample the RXD input line by either 8 or 16 times the baud rate clock, as selected by the
Oversampling Mode bit (MR.OVER). If the line is zero for half a bit period (four or eight consecu-
tive samples, respectively), a start bit will be assumed, and the following 8th or 16th sample will
determine the logical value on the line, in effect resulting in bit values being determined at the
middle of the bit period.
The number of data bits, endianess, parity mode, and stop bits are selected by the same bits
and fields as for the transmitter (MR.CHRL, MODE9, MSBF, PAR, and NBSTOP). The synchro-
Oversampling
Sampling
16x Clock
th
point
RXD
’s after the expected edge, the current period will be prolonged by a 16
Manchester
Manchester
Manchester
encoded
encoded
encoded
th
data
data
data
’s early, the current period will be shortened by a 16
Preamble Length
Synchro.
Txd
Txd
Txd
Error
is set to 0
Synchro.
SFD
SFD
SFD
Jump
DATA
One bit start frame delimiter
Expected edge
Tolerance
start frame delimiter
start frame delimiter
DATA
DATA
Command Sync
Jump
Sync
Data Sync
Synchro.
th
th
. If the event is two
Error
clock cycle from
th
.
307
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