AT32UC3A464 Atmel Corporation, AT32UC3A464 Datasheet - Page 70

• Manufacturer Part Number: AT32UC3A464
• Manufacturer: Atmel Corporation

Specifications of AT32UC3A464

• Flash (kbytes): 64 Kbytes
• Pin Count: 100
• Max. Operating Frequency: 66 MHz
• Cpu: 32-bit AVR
• Hardware Qtouch Acquisition: No
• Usb Transceiver: 1
• Usb Speed: Hi-Speed
• Usb Interface: Device + OTG
• Spi: 6
• Twi (i2c): 2
• Uart: 4
• Ssc: 1
• Sd / Emmc: 2
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 8
• Adc Resolution (bits): 10
• Resistive Touch Screen: No
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 128
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: Yes
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 3.0 to 3.6
• Operating Voltage (vcc): 3.0 to 3.6
• Fpu: No
• Timers: 6
• Output Compare Channels: 6
• Input Capture Channels: 6
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

8.3.1.5
8.3.1.6
8.3.1.7
70
AVR32
Bus Error Exception on Data Access
Bus Error Exception on Instruction Fetch
NMI Exception
The Bus Error on Data Access exception is generated when the data bus detects an error condi-
tion. This exception is caused by events unrelated to the instruction stream, or by data written to
the cache write-buffers many cycles ago. Therefore, execution can not be resumed in a safe
way after this exception. The value placed in RAR_EX is unrelated to the operation that caused
the exception. The exception handler is responsible for performing the appropriate action.
The Bus Error on Instruction Fetch exception is generated when the data bus detects an error
condition. This exception is caused by events related to the instruction stream. Therefore, exe-
cution can be restarted in a safe way after this exception, assuming that the condition that
caused the bus error is dealt with.
The NMI exception is generated when the NMI input line to the core is asserted. The NMI excep-
tion can not be masked by the SR[GM] bit. However, the core ignores the NMI input line when
processing an NMI Exception (the SR[M2:M0] bits are B’111). This guarantees serial execution
of NMI Exceptions, and simplifies the NMI hardware and software mechanisms.
Since the NMI exception is unrelated to the instruction stream, the instructions in the pipeline are
allowed to complete. After finishing the NMI exception routine, execution should continue at the
instruction following the last completed instruction in the instruction stream.
*(--SP
*(--SP
SR[R] = 0;
SR[J] = 0;
SR[M2:M0] = B’110;
SR[EM] = 1;
SR[GM] = 1;
PC = EVBA + 0x08;
*(--SP
*(--SP
SR[R] = 0;
SR[J] = 0;
SR[M2:M0] = B’110;
SR[EM] = 1;
SR[GM] = 1;
PC = EVBA + 0x0C;
*(--SP
*(--SP
SR[R] = 0;
SR[J] = 0;
SR[M2:M0] = B’111;
SR[EM] = 1;
SR[GM] = 1;
PC = EVBA + 0x10;
SYS
SYS
SYS
SYS
SYS
SYS
) = PC of first non-issued instruction;
) = SR;
) = PC of first non-issued instruction;
) = SR;
) = PC of first noncompleted instruction;
) = SR;
32000D–04/2011