AT32UC3A464 Atmel Corporation, AT32UC3A464 Datasheet - Page 52

• Manufacturer Part Number: AT32UC3A464
• Manufacturer: Atmel Corporation

Specifications of AT32UC3A464

• Flash (kbytes): 64 Kbytes
• Pin Count: 100
• Max. Operating Frequency: 66 MHz
• Cpu: 32-bit AVR
• Hardware Qtouch Acquisition: No
• Usb Transceiver: 1
• Usb Speed: Hi-Speed
• Usb Interface: Device + OTG
• Spi: 6
• Twi (i2c): 2
• Uart: 4
• Ssc: 1
• Sd / Emmc: 2
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 8
• Adc Resolution (bits): 10
• Resistive Touch Screen: No
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 128
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: Yes
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 3.0 to 3.6
• Operating Voltage (vcc): 3.0 to 3.6
• Fpu: No
• Timers: 6
• Output Compare Channels: 6
• Input Capture Channels: 6
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

6.2.1.1
52
AVR32
MPU Address Register - MPUARn
tem Register space, their addresses are presented in
accessed with the mtsr and mfsr instructions.
The MPU interface registers are shown below. The suffix n can have the range 0-7, indicating
which region the register is associated with.
Figure 6-1.
A MPU Address register is implemented for each of the 8 protection regions. The MPUAR regis-
ters specify the start address and size of the regions. The start address must be aligned so that
its alignment corresponds to the size of the region. The minimum allowable size of a region is 4
KB, so only bits 31:12 in the base address needs to be specified. The other bits are always 0.
Each MPUAR also has a valid bit that specifies if the protection region is valid. Only valid regions
are considered in the protection testing.
The MPUAR register consists of the following fields:
• Base address - The start address of the region. The minimum size of a region is 4KB, so only
MPUARn
MPUPSRn
MPUCRA / MPUCRB
MPUBRA / MPUBRB
MPUAPRA / MPUAPRB
MPUCR
the 20 most significant bits in the base address needs to be specified. The 12 lowermost
base address bits are implicitly set to 0. If protection regions larger than 4 KB is used, the
user must write the appropriate bits in Base address to 0, so that the base address is aligned
to the size of the region. Otherwise, the result is UNDEFINED.
31
31
31
31
31
31
AP7
28
The MPU interface registers
27
AP6
24
-
23
Base Address
AP5
20
-
-
19
AP4
16
16 15
-
15
14
AP3
13 12 11 10
“System registers” on page
12
11
12
AP2
11
9
8 7 6
8 7 6
8 7 6
8
-
7
6
AP1
5
5
5
5
4 3 2 1
4 3 2 1
4 3 2 1
4
Size
3
14. They are
32000D–04/2011
AP0
1
1
0
V
0
0
0
0
0
E