AT32UC3A464 Atmel Corporation, AT32UC3A464 Datasheet - Page 114

• Manufacturer Part Number: AT32UC3A464
• Manufacturer: Atmel Corporation

Specifications of AT32UC3A464

• Flash (kbytes): 64 Kbytes
• Pin Count: 100
• Max. Operating Frequency: 66 MHz
• Cpu: 32-bit AVR
• Hardware Qtouch Acquisition: No
• Usb Transceiver: 1
• Usb Speed: Hi-Speed
• Usb Interface: Device + OTG
• Spi: 6
• Twi (i2c): 2
• Uart: 4
• Ssc: 1
• Sd / Emmc: 2
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 8
• Adc Resolution (bits): 10
• Resistive Touch Screen: No
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 128
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: Yes
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 3.0 to 3.6
• Operating Voltage (vcc): 3.0 to 3.6
• Fpu: No
• Timers: 6
• Output Compare Channels: 6
• Input Capture Channels: 6
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

9.3.9
9.3.9.1
Table 9-9.
9.3.9.2
Table 9-10.
114
Mnemonics
mov
mov{cond4}
movh
Mnemonics
ld.ub
ld.ub{cond4}
ld.sb
ld.sb{cond4}
ld.uh
ld.uh{cond4}
AVR32
Data Transfer
Move/Load Immediate operations
Load/Store operations
Move/Load Immediate Operations
Load/Store Operations
C
E
C
E
E
E
C
C
C
E
E
E
E
E
E
C
C
C
E
E
E
Operands / Syntax
Rd, imm
Rd, imm
Rd, Rs
Rd, Rs
Rd, imm
Rd, imm
Operands / Syntax
Rd, Rp++
Rd, --Rp
Rd, Rp[disp]
Rd, Rp[disp]
Rd, Rb[Ri<<sa]
Rd, Rp[disp]
Rd, Rp[disp]
Rd, Rb[Ri<<sa]
Rd, Rp[disp]
Rd, Rp++
Rd, --Rp
Rd, Rp[disp]
Rd, Rp[disp]
Rd, Rb[Ri<<sa]
Rd, Rp[disp]
Description
Load immediate into register.
Copy register.
Copy register if condition is true
Load immediate into register if condition is
true
Load immediate into high halfword of
register.
Description
Load unsigned byte with post-increment.
Load unsigned byte with pre-decrement.
Load unsigned byte with displacement.
Indexed Load unsigned byte.
Load unsigned byte with displacement if
condition satisfied.
Load signed byte with displacement.
Indexed Load signed byte.
Load signed byte with displacement if
condition satisfied.
Load unsigned halfword with post-
increment.
Load unsigned halfword with pre-
decrement.
Load unsigned halfword with
displacement.
Indexed Load unsigned halfword.
Load unsigned halfword with
displacement if condition satisfied.
Operation
Rd ← ZE(*(Rp++))
Rd ← ZE(*(--Rp))
Rd ← ZE(*(Rp+ZE(disp3)))
Rd ← ZE(*(Rp+SE(disp16)))
Rd ← ZE(*(Rb+(Ri << sa2)))
if {cond4}
Rd ← ZE(*(Rp+ZE(disp9)))
Rd ← SE(*(Rp+SE(disp16)))
Rd ← SE(*(Rb+(Ri << sa2)))
if {cond4}
Rd ← SE(*(Rp+ZE(disp9)))
Rd ← ZE(*(Rp++))
Rd ← ZE(*(--Rp))
Rd ← ZE(*(Rp+(ZE(disp3)<<1)))
Rd ← ZE(*(Rp+(SE(disp16))))
Rd ← ZE(*(Rb+(Ri << sa2)))
if {cond4}
Rd ← ZE(*(Rp+ZE(disp9<<1)))
Operation
Rd ← SE(imm8)
Rd ← SE(imm21)
Rd ← Rs
if (cond4) Rd ← Rs
if (cond4) Rd ← SE(imm8)
Rd ← imm16<<16
32000D–04/2011
Rev
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