AT32UC3A464 Atmel Corporation, AT32UC3A464 Datasheet - Page 240

• Manufacturer Part Number: AT32UC3A464
• Manufacturer: Atmel Corporation

Specifications of AT32UC3A464

• Flash (kbytes): 64 Kbytes
• Pin Count: 100
• Max. Operating Frequency: 66 MHz
• Cpu: 32-bit AVR
• Hardware Qtouch Acquisition: No
• Usb Transceiver: 1
• Usb Speed: Hi-Speed
• Usb Interface: Device + OTG
• Spi: 6
• Twi (i2c): 2
• Uart: 4
• Ssc: 1
• Sd / Emmc: 2
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 8
• Adc Resolution (bits): 10
• Resistive Touch Screen: No
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 128
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: Yes
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 3.0 to 3.6
• Operating Voltage (vcc): 3.0 to 3.6
• Fpu: No
• Timers: 6
• Output Compare Channels: 6
• Input Capture Channels: 6
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

240
AVR32
MULSATRNDWH.W – Multiply Word and Halfword with Saturation and
Rounding into Word
Architecture revision:
Architecture revision1 and higher.
Description
Multiplies the word register with the halfword register specified, rounds the upper 32 bits of the
result and stores it in the destination word-register. The halfword register is selected as either
the high or low part of Ry. Since the most significant part of the product is stored, no overflow will
occur. If the two operands equals -1, the result is saturated to the largest positive 32-bit fractional
number.
Operation:
I.
Syntax:
I.
Operands:
I.
Status Flags:
Opcode:
Example:
0x4000) >> 15
31
1
15
0
operand1 = Rx;
If (Ry-part == t) then operand2 = SE(Ry[31:16]) else operand2 = SE(Ry[15:0]);
If ((operand1 == 0x8000_0000) && (operand2 == 0x8000))
else
mulsatrndwh.w Rd, Rx, Ry:<part>
{d, x, y} ∈ {0, 1, …, 15}
part ∈ {t,b}
Q:
V:
N:
Z:
C:
mulsatrndwh.w R10, R2, R3b will perform R10 ← (Sat( R2[31:16] × SE(R3[15:0]) ) +
1
0
29
1
0
Rd ← 0x7FFF_FFFF;
Rd ← SE( ((operand1 × operand2) + 0x4000 ) >> 15 );
Set if saturation occurred, or previously set.
Not affected.
Not affected.
Not affected.
Not affected.
12
28
0
11
1
Rx
0
25
1
8
24
0
1
7
0
1
0
0
5
0
0
4
Y
20
0
3
19
Ry
Rd
32000D–04/2011
0
16