AT32UC3A464 Atmel Corporation, AT32UC3A464 Datasheet - Page 51

• Manufacturer Part Number: AT32UC3A464
• Manufacturer: Atmel Corporation

Specifications of AT32UC3A464

• Flash (kbytes): 64 Kbytes
• Pin Count: 100
• Max. Operating Frequency: 66 MHz
• Cpu: 32-bit AVR
• Hardware Qtouch Acquisition: No
• Usb Transceiver: 1
• Usb Speed: Hi-Speed
• Usb Interface: Device + OTG
• Spi: 6
• Twi (i2c): 2
• Uart: 4
• Ssc: 1
• Sd / Emmc: 2
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 8
• Adc Resolution (bits): 10
• Resistive Touch Screen: No
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 128
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: Yes
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 3.0 to 3.6
• Operating Voltage (vcc): 3.0 to 3.6
• Fpu: No
• Timers: 6
• Output Compare Channels: 6
• Input Capture Channels: 6
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

6. Memory Protection Unit
6.1
6.2
6.2.1
32000D–04/2011
Memory map in systems with MPU
Understanding the MPU
MPU interface registers
The AVR32 architecture defines an optional Memory Protection Unit (MPU). This is a simpler
alternative to a full MMU, while at the same time allowing memory protection. The MPU allows
the user to divide the memory space into different protection regions. These protection regions
have a user-defined size, and starts at a user-defined address. The different regions can have
different cacheability attributes and bufferability attributes. Each region is divided into 16 subre-
gions, each of these subregions can have one of two possible sets of access permissions.
The MPU does not perform any address translation.
An AVR32 implemetation with a MPU has a flat, unsegmented memory space. Access permis-
sions are given only by the different protection regions.
The AVR32 Memory Protection Unit (MPU) is responsible for checking that memory transfers
have the correct permissions to complete. If a memory access with unsatisfactory privileges is
attempted, an exception is generated and the access is aborted. If an access to a memory
address that does not reside in any protection region is attempted, an exception is generated
and the access is aborted.
The user is able to allow different privilege levels to different blocks of memory by configuring a
set of registers. Each such block is called a protection region. Each region has a user-program-
mable start address and size. The MPU allows the user to program 8 different protection
regions. Each of these regions have 16 sub-regions, which can have different access permis-
sions, cacheability and bufferability.
The “DMMU SZ” fields in the CONFIG1 system register identifies the number of implemented
protection regions, and therefore also the number of MPU registers. A system with caches also
have MPU cacheability and bufferability registers.
A protection region can be from 4 KB to 4 GB in size, and the size must be a power of two. All
regions must have a start address that is aligned to an address corresponding to the size of the
region. If the region has a size of 8 KB, the 13 lowest bits in the start address must be 0. Failing
to do so will result in UNDEFINED behaviour. Since each region is divided into 16 sub-regions,
each sub-region is 256 B to 256 MB in size.
When an access hits into a memory region set up by the MPU, hardware proceeds to determine
which subregion the access hits into. This information is used to determine whether the access
p e r m i s s io n s f o r t h e s u b r e g i o n a r e g iv e n i n M P U A P R A/ M PU B R A / M P U C R A o r i n
MPUAPRB/MPUBRB/MPUCRB.
If an access does not hit in any region, the transfer is aborted and an exception is generated.
The MPU is enabled by writing setting the E bit in the MPUCR register. The E bit is cleared after
reset. If the MPU is disabled, all accesses are treated as uncacheable, unbufferable and will not
generate any access violations. Before setting the E bit, at least one valid protection region must
be defined.
The following registers are used to control the MPU, and provide the interface between the MPU
and the operating system, see
Figure 6-1 on page
52. All the registers are mapped into the Sys-
AVR32
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