AT32UC3A464 Atmel Corporation, AT32UC3A464 Datasheet - Page 54

• Manufacturer Part Number: AT32UC3A464
• Manufacturer: Atmel Corporation

Specifications of AT32UC3A464

• Flash (kbytes): 64 Kbytes
• Pin Count: 100
• Max. Operating Frequency: 66 MHz
• Cpu: 32-bit AVR
• Hardware Qtouch Acquisition: No
• Usb Transceiver: 1
• Usb Speed: Hi-Speed
• Usb Interface: Device + OTG
• Spi: 6
• Twi (i2c): 2
• Uart: 4
• Ssc: 1
• Sd / Emmc: 2
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 8
• Adc Resolution (bits): 10
• Resistive Touch Screen: No
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 128
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: Yes
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 3.0 to 3.6
• Operating Voltage (vcc): 3.0 to 3.6
• Fpu: No
• Timers: 6
• Output Compare Channels: 6
• Input Capture Channels: 6
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

6.2.1.3
6.2.1.4
6.2.1.5
6.2.1.6
6.2.2
6.2.2.1
54
AVR32
MPU exception handling
MPU Cacheable Register A / B- MPUCRA / MPUCRB
MPU Bufferable Register A / B- MPUBRA / MPUBRB
MPU Access Permission Register A / B - MPUAPRA / MPUAPRB
MPU Control Register - MPUCR
ITLB Protection Violation
The MPUCR registers have one bit per region, indicating if the region is cacheable. If the corre-
sponding bit is set, the region is cacheable. The register is written to 0 upon reset.
AVR32UC implementations may optionally choose not to implement the MPUCR registers.
The MPUBR registers have one bit per region, indicating if the region is bufferable. If the corre-
sponding bit is set, the region is bufferable. The register is written to 0 upon reset.
AVR32UC implementations may optionally choose not to implement the MPUBR registers.
The MPUAPR registers indicate the access permissions for each region. The MPUAPR is writ-
ten to 0 upon reset. The possible access permissions are shown in
Table 6-3.
The MPUCR controls the operation of the MPU. The MPUCR has only one field:
This chapter describes the exceptions that can be signalled by the MPU.
An ITLB protection violation is issued if an instruction fetch violates access permissions. The vio-
lating instruction is not executed. The address of the failing instruction is placed on the system
stack.
AP
B’0000
B’0001
B’0010
B’0011
B’0100
B’0101
B’0110
B’0111
B’1000
B’1001
B’1010
Other
• E - Enable. If set, the MPU address checking is enabled. If cleared, the MPU address
checking is disabled and no exceptions will be generated by the MPU.
Access permissions implied by the APn bits
Privileged mode
Read
Read / Execute
Read / Write
Read / Write / Execute
Read
Read / Execute
Read / Write
Read / Write / Execute
Read / Write
Read / Write
None
UNDEFINED
Unprivileged mode
None
None
None
None
Read
Read / Execute
Read / Write
Read / Write / Execute
Read
Read / Execute
None
UNDEFINED
Table 6-3 on page
32000D–04/2011
54.