AT32UC3A4128S Atmel Corporation, AT32UC3A4128S Datasheet - Page 889
AT32UC3A4128S
Manufacturer Part Number
AT32UC3A4128S
Description
Manufacturer
Atmel Corporation
Datasheets
1.AT32UC3A0128.pdf
(377 pages)
2.AT32UC3A0128.pdf
(33 pages)
3.AT32UC3A0128.pdf
(159 pages)
4.AT32UC3A3128.pdf
(91 pages)
5.AT32UC3A3128.pdf
(1012 pages)
Specifications of AT32UC3A4128S
Flash (kbytes)
128 Kbytes
Pin Count
100
Max. Operating Frequency
66 MHz
Cpu
32-bit AVR
Hardware Qtouch Acquisition
No
Usb Transceiver
1
Usb Speed
Hi-Speed
Usb Interface
Device + OTG
Spi
6
Twi (i2c)
2
Uart
4
Sd / Emmc
2
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
8
Adc Resolution (bits)
10
Resistive Touch Screen
No
Temp. Sensor
No
Crypto Engine
AES
Sram (kbytes)
128
Self Program Memory
YES
Dram Memory
No
Nand Interface
Yes
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
3.0 to 3.6
Operating Voltage (vcc)
3.0 to 3.6
Fpu
No
Mpu / Mmu
Yes / No
Timers
6
Output Compare Channels
6
Input Capture Channels
6
32khz Rtc
Yes
Calibrated Rc Oscillator
Yes
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- AT32UC3A0128 PDF datasheet
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- AT32UC3A0128 PDF datasheet #3
- AT32UC3A3128 PDF datasheet #4
- AT32UC3A3128 PDF datasheet #5
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32.4.4
32.4.4.1
32.4.4.2
32072G–11/2011
Security Features
Countermeasures
Unspecified register access detection
The AES also features hardware countermeasures that can be useful to protect data against Dif-
ferential Power Analysis (DPA) attacks.
These countermeasures can be enabled through the Countermeasure Type field in the MR reg-
ister (MR.CTYPE). This field is write-only, and all changes to it are taken into account if, at the
same time, the Countermeasure Key field in the Mode Register (MR.CKEY) is correctly written
(see the Mode Register (MR) description in
Note:
By default, all the countermeasures are enabled.
The best throughput is achieved with all the countermeasures disabled. On the other hand, the
best protection is achieved with all of them enabled.
The Random Number Generator Seed Loading bit in the CR register (CR.LOADSEED) allows a
new seed to be loaded in the embedded random number generator used for the different
countermeasures.
When an unspecified register access occurs, the Unspecified Register Detection Status bit in
the ISR register (ISR.URAD) is set to one. Its source is then reported in the Unspecified Register
Access Type field in the ISR register (ISR.URAT). Only the last unspecified register access is
available through the ISR.URAT field.
Several kinds of unspecified register accesses can occur when:
The ISR.URAD bit and the ISR.URAT field can only be reset by the Software Reset bit in the CR
register (CR.SWRST).
• Writing the IDATAnR registers during the data processing in DMA mode
• Reading the ODATAnR registers during data processing
• Writing the MR register during data processing
• Reading the ODATAnR registers during sub-keys generation
• Writing the MR register during sub-keys generation
• Reading an write-only register
Enabling countermeasures has an impact on the AES encryption/decryption throughput.
Section
32.5.2).
889
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