AT32UC3A4128S Atmel Corporation, AT32UC3A4128S Datasheet - Page 766
AT32UC3A4128S
Manufacturer Part Number
AT32UC3A4128S
Description
Manufacturer
Atmel Corporation
Datasheets
1.AT32UC3A0128.pdf
(377 pages)
2.AT32UC3A0128.pdf
(33 pages)
3.AT32UC3A0128.pdf
(159 pages)
4.AT32UC3A3128.pdf
(91 pages)
5.AT32UC3A3128.pdf
(1012 pages)
Specifications of AT32UC3A4128S
Flash (kbytes)
128 Kbytes
Pin Count
100
Max. Operating Frequency
66 MHz
Cpu
32-bit AVR
Hardware Qtouch Acquisition
No
Usb Transceiver
1
Usb Speed
Hi-Speed
Usb Interface
Device + OTG
Spi
6
Twi (i2c)
2
Uart
4
Sd / Emmc
2
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
8
Adc Resolution (bits)
10
Resistive Touch Screen
No
Temp. Sensor
No
Crypto Engine
AES
Sram (kbytes)
128
Self Program Memory
YES
Dram Memory
No
Nand Interface
Yes
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
3.0 to 3.6
Operating Voltage (vcc)
3.0 to 3.6
Fpu
No
Mpu / Mmu
Yes / No
Timers
6
Output Compare Channels
6
Input Capture Channels
6
32khz Rtc
Yes
Calibrated Rc Oscillator
Yes
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- AT32UC3A0128 PDF datasheet
- AT32UC3A0128 PDF datasheet #2
- AT32UC3A0128 PDF datasheet #3
- AT32UC3A3128 PDF datasheet #4
- AT32UC3A3128 PDF datasheet #5
- Current page: 766 of 1012
- Download datasheet (16Mb)
• ACPA: RA Compare Effect on TIOA
• WAVE
• WAVSEL: Waveform Selection
• ENETRG: External Event Trigger Enable
• EEVT: External Event Selection
Note:
• EEVTEDG: External Event Edge Selection
• CPCDIS: Counter Clock Disable with RC Compare
32072G–11/2011
EEVTEDG
WAVSEL
ACPA
EEVT
0
1
2
3
0
1
2
3
0
1
2
3
1: Waveform mode is enabled.
0: Waveform mode is disabled (Capture mode is enabled).
1: The external event resets the counter and starts the counter clock.
0: The external event has no effect on the counter and its clock. In this case, the selected external event only controls the TIOA
output.
0
1
2
3
1. If TIOB is chosen as the external event signal, it is configured as an input and no longer generates waveforms and subse-
1: Counter clock is disabled when counter reaches RC.
0: Counter clock is not disabled when counter reaches RC.
quently no IRQs .
Effect
UP mode without automatic trigger on RC Compare
UPDOWN mode without automatic trigger on RC Compare
UP mode with automatic trigger on RC Compare
UPDOWN mode with automatic trigger on RC Compare
Edge
none
rising edge
falling edge
each edge
Effect
none
set
clear
toggle
Signal selected as external event
TIOB
XC0
XC1
XC2
TIOB Direction
input
output
output
output
(1)
766
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