AT32UC3A4128S Atmel Corporation, AT32UC3A4128S Datasheet - Page 224
AT32UC3A4128S
Manufacturer Part Number
AT32UC3A4128S
Description
Manufacturer
Atmel Corporation
Datasheets
1.AT32UC3A0128.pdf
(377 pages)
2.AT32UC3A0128.pdf
(33 pages)
3.AT32UC3A0128.pdf
(159 pages)
4.AT32UC3A3128.pdf
(91 pages)
5.AT32UC3A3128.pdf
(1012 pages)
Specifications of AT32UC3A4128S
Flash (kbytes)
128 Kbytes
Pin Count
100
Max. Operating Frequency
66 MHz
Cpu
32-bit AVR
Hardware Qtouch Acquisition
No
Usb Transceiver
1
Usb Speed
Hi-Speed
Usb Interface
Device + OTG
Spi
6
Twi (i2c)
2
Uart
4
Sd / Emmc
2
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
8
Adc Resolution (bits)
10
Resistive Touch Screen
No
Temp. Sensor
No
Crypto Engine
AES
Sram (kbytes)
128
Self Program Memory
YES
Dram Memory
No
Nand Interface
Yes
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
3.0 to 3.6
Operating Voltage (vcc)
3.0 to 3.6
Fpu
No
Mpu / Mmu
Yes / No
Timers
6
Output Compare Channels
6
Input Capture Channels
6
32khz Rtc
Yes
Calibrated Rc Oscillator
Yes
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- AT32UC3A0128 PDF datasheet
- AT32UC3A0128 PDF datasheet #2
- AT32UC3A0128 PDF datasheet #3
- AT32UC3A3128 PDF datasheet #4
- AT32UC3A3128 PDF datasheet #5
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Figure 16-4. Write Burst, 16-bit SDRAM Access
16.7.3
32072G–11/2011
SDRAMC_A[12:0]
D[15:0]
SDWE
SDCS
SDCK
SDRAM Controller Read Cycle
RAS
CAS
The SDRAMC allows burst access, incremental burst of unspecified length or single access. In
all cases, the SDRAMC keeps track of the active row in each bank, thus maximizing perfor-
mance of the SDRAM. If row and bank addresses do not match the previous row/bank address,
then the SDRAMC automatically generates a precharge command, activates the new row and
starts the read command. To comply with the SDRAM timing parameters, additional clock cycles
on SDCK are inserted between precharge and active (t
read (t
read command, additional wait states are generated to comply with the CAS latency (one, two,
or three clock delays specified in the CR register).
For a single access or an incremented burst of unspecified length, the SDRAMC anticipates the
next access. While the last value of the column is returned by the SDRAMC on the bus, the
SDRAMC anticipates the read to the next column and thus anticipates the CAS latency. This
reduces the effect of the CAS latency on the internal bus.
For burst access of specified length (4, 8, 16 words), access is not anticipated. This case leads
to the best performance. If the burst is broken (border, busy mode, etc.), the next access is han-
dled as an incrementing burst of unspecified length.
Row n
t
RCD
RCD
= 3
) commands. These two parameters are set in the CR register of the SDRAMC. After a
Col a
Dna
Col b
Dnb
Col c
Dnc
Col d
Dnd
Col e
Dne
Col f
Dnf
Col g
Dng
RP
) commands and between active and
Col h Col i
Dnh
Dni
Col j
Dnj
Col k
Dnk
Col l
Dnl
224
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