AT32UC3A4128S Atmel Corporation, AT32UC3A4128S Datasheet - Page 189
AT32UC3A4128S
Manufacturer Part Number
AT32UC3A4128S
Description
Manufacturer
Atmel Corporation
Datasheets
1.AT32UC3A0128.pdf
(377 pages)
2.AT32UC3A0128.pdf
(33 pages)
3.AT32UC3A0128.pdf
(159 pages)
4.AT32UC3A3128.pdf
(91 pages)
5.AT32UC3A3128.pdf
(1012 pages)
Specifications of AT32UC3A4128S
Flash (kbytes)
128 Kbytes
Pin Count
100
Max. Operating Frequency
66 MHz
Cpu
32-bit AVR
Hardware Qtouch Acquisition
No
Usb Transceiver
1
Usb Speed
Hi-Speed
Usb Interface
Device + OTG
Spi
6
Twi (i2c)
2
Uart
4
Sd / Emmc
2
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
8
Adc Resolution (bits)
10
Resistive Touch Screen
No
Temp. Sensor
No
Crypto Engine
AES
Sram (kbytes)
128
Self Program Memory
YES
Dram Memory
No
Nand Interface
Yes
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
3.0 to 3.6
Operating Voltage (vcc)
3.0 to 3.6
Fpu
No
Mpu / Mmu
Yes / No
Timers
6
Output Compare Channels
6
Input Capture Channels
6
32khz Rtc
Yes
Calibrated Rc Oscillator
Yes
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- AT32UC3A0128 PDF datasheet
- AT32UC3A0128 PDF datasheet #2
- AT32UC3A0128 PDF datasheet #3
- AT32UC3A3128 PDF datasheet #4
- AT32UC3A3128 PDF datasheet #5
- Current page: 189 of 1012
- Download datasheet (16Mb)
15.6.4.5
32072G–11/2011
Write mode
•Null delay setup and hold
•Null pulse
•Write is controlled by NWE (MODE.WRITEMODE = 1)
If null setup parameters are programmed for NWE and/or NCS, NWE and/or NCS remain active
continuously in case of consecutive write cycles in the same memory (see
189). However, for devices that perform write operations on the rising edge of NWE or NCS,
such as SRAM, either a setup or a hold must be programmed.
Figure 15-12. Null Setup and Hold Values of NCS and NWE in Write Cycle
Programming null pulse is not permitted. Pulse must be at least written to one. A null value leads
to unpredictable behavior.
The Write Mode bit in the MODE register (MODE.WRITEMODE) of the corresponding chip
select indicates which signal controls the write operation.
Figure 15-13 on page 190
equal to one. The data is put on the bus during the pulse and hold steps of the NWE signal. The
internal data buffers are turned out after the NWESETUP time, and until the end of the write
cycle, regardless of the programmed waveform on NCS.
NBS0, NBS1,
A[AD_MSB:2]
NWE0, NWE1
A0, A1
CLK_SMC
NWE,
NCS
D[15:0]
NCSWRSETUP
NWECYCLE
NWESETUP
shows the waveforms of a write operation with MODE.WRITEMODE
NWEPULSE
NCSWRPULSE
NWECYCLE
NCSWRPULSE
NWECYCLE
NWEPULSE
Figure 15-12 on page
189
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