AT32UC3A0512AU Atmel Corporation, AT32UC3A0512AU Datasheet - Page 625

• Manufacturer Part Number: AT32UC3A0512AU
• Manufacturer: Atmel Corporation

Specifications of AT32UC3A0512AU

• Flash (kbytes): 512 Kbytes
• Pin Count: 144
• Max. Operating Frequency: 66 MHz
• Cpu: 32-bit AVR
• # Of Touch Channels: 32
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 109
• Ext Interrupts: 109
• Usb Transceiver: 1
• Usb Speed: Full Speed
• Usb Interface: Device + OTG
• Spi: 6
• Twi (i2c): 1
• Uart: 4
• Ssc: 1
• Ethernet: 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 8
• Adc Resolution (bits): 10
• Adc Speed (ksps): 384
• Resistive Touch Screen: No
• Dac Channels: 2
• Dac Resolution (bits): 16
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 64
• Self Program Memory: YES
• External Bus Interface: 1
• Dram Memory: sdram
• Nand Interface: No
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 3.0-3.6 or (1.65-1.95+3.0-3.6)
• Operating Voltage (vcc): 3.0-3.6 or (1.65-1.95+3.0-3.6)
• Fpu: No
• Mpu / Mmu: Yes / No
• Timers: 10
• Output Compare Channels: 16
• Input Capture Channels: 6
• Pwm Channels: 13
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

32058K AVR32-01/12
• OVERFIE: Overflow Interrupt Enable
Set by software (by setting the OVERFIES bit) to enable the Overflow interrupt (OVERFIE).
Clear by software (by setting the OVERFIEC bit) to disable the Overflow interrupt (OVERFIE).
• RXSTALLDE: Received STALLed Interrupt Enable
Set by software (by setting the RXSTALLDES bit) to enable the Received STALLed interrupt (RXSTALLDE).
Clear by software (by setting the RXSTALLDEC bit) to disable the Received STALLed interrupt (RXSTALLDE).
• CRCERRE: CRC Error Interrupt Enable
Set by software (by setting the CRCERRES bit) to enable the CRC Error interrupt (CRCERRE).
Clear by software (by setting the CRCERREC bit) to disable the CRC Error interrupt (CRCERRE).
• SHORTPACKETIE: Short Packet Interrupt Enable
Set by software (by setting the SHORTPACKETES bit) to enable the Short Packet interrupt (SHORTPACKETIE).
Clear by software (by setting the SHORTPACKETEC bit) to disable the Short Packet interrupt (SHORTPACKETE).
• NBUSYBKE: Number of Busy Banks Interrupt Enable
Set by software (by setting the NBUSYBKES bit) to enable the Number of Busy Banks interrupt (NBUSYBKE).
Clear by software (by setting the NBUSYBKEC bit) to disable the Number of Busy Banks interrupt (NBUSYBKE).
• FIFOCON: FIFO Control
For OUT and SETUP Pipe :
Set by hardware when the current bank is free, at the same time than TXOUTI or TXSTPI.
Clear by software (by setting the FIFOCONC bit) to send the FIFO data and to switch the bank.
For IN Pipe:
• PDISHDMA: Pipe Interrupts Disable HDMA Request Enable
See EPDISHDMA (UECONX register).
• PFREEZE: Pipe Freeze
Set by software (by setting the PFREEZES bit) to Freeze the Pipe requests generation.
Clear by software (by setting the PFREEZEC bit) to enable the Pipe request generation.
This bit is set by hardware when:
- the pipe is not configured
- a STALL handshake has been received on this Pipe
- An error occurs on the Pipe (PERR = 1)
- (INRQ+1) In requests have been processed
This bit is set at 1 by hardware after a Pipe reset or a Pipe enable.
• RSTDT: Reset Data Toggle
Set by software (by setting the RSTDTS bit) to reset the Data Toggle to its initial value for the current Pipe.
Cleared by hardware when proceed.
Set by hardware when a new IN message is stored in the current bank, at the same time than RXINI.
Clear by software (by setting the FIFOCONC bit) to free the current bank and to switch to the next bank.
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