AT32UC3A0512AU Atmel Corporation, AT32UC3A0512AU Datasheet - Page 513

• Manufacturer Part Number: AT32UC3A0512AU
• Manufacturer: Atmel Corporation

Specifications of AT32UC3A0512AU

• Flash (kbytes): 512 Kbytes
• Pin Count: 144
• Max. Operating Frequency: 66 MHz
• Cpu: 32-bit AVR
• # Of Touch Channels: 32
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 109
• Ext Interrupts: 109
• Usb Transceiver: 1
• Usb Speed: Full Speed
• Usb Interface: Device + OTG
• Spi: 6
• Twi (i2c): 1
• Uart: 4
• Ssc: 1
• Ethernet: 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 8
• Adc Resolution (bits): 10
• Adc Speed (ksps): 384
• Resistive Touch Screen: No
• Dac Channels: 2
• Dac Resolution (bits): 16
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 64
• Self Program Memory: YES
• External Bus Interface: 1
• Dram Memory: sdram
• Nand Interface: No
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 3.0-3.6 or (1.65-1.95+3.0-3.6)
• Operating Voltage (vcc): 3.0-3.6 or (1.65-1.95+3.0-3.6)
• Fpu: No
• Mpu / Mmu: Yes / No
• Timers: 10
• Output Compare Channels: 16
• Input Capture Channels: 6
• Pwm Channels: 13
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

32058K AVR32-01/12
30.7.2.6
30.7.2.7
30.7.2.8
30.7.2.9
Suspend and Wake-Up
Address Setup
Detach
Remote Wake-Up
See
The USB device address is set up according to the USB protocol:
Once the USB device address is configured, the controller filters the packets to only accept
those targeting the address stored in UADD.
UADD and ADDEN shall not be written all at once.
UADD and ADDEN are cleared by hardware:
When UADD or ADDEN is cleared, the default device address 0 is used.
When an idle USB bus state has been detected for 3 ms, the controller raises the Suspend inter-
rupt (SUSP). The firmware may then set the FRZCLK bit to reduce power consumption. The
MCU can also enter the Idle or Frozen sleep mode to lower again power consumption.
To recover from the Suspend mode, the firmware should wait for the Wake-Up interrupt
(WAKEUP), which is raised when a non-idle event is detected, then clear FRZCLK.
As the WAKEUP interrupt is raised when a non-idle event is detected, it can occur whether the
controller is in the Suspend mode or not. The SUSP and WAKEUP interrupts are thus indepen-
dent of each other except that one’s flag is cleared by hardware when the other is raised.
The reset value of the DETACH bit is 1.
It is possible to initiate a device re-enumeration simply by setting then clearing DETACH.
DETACH acts on the pull-up connections of the D+ and D- pads. See
page 506
The Remote Wake-Up request (also known as Upstream Resume) is the only one the device
may send on its own initiative, but the device should have beforehand been allowed to by a
DEVICE_REMOTE_WAKEUP request from the host.
• First, the USB controller must have detected a “Suspend” state on the bus, i.e. the Remote
•after all kinds of resets, the USB device address is 0;
•the host starts a SETUP transaction with a SET_ADDRESS(addr) request;
•the firmware records this address into the UADD bit-field, leaving the ADDEN bit cleared, so
•the firmware sends a zero-length IN packet from the control endpoint;
•the firmware enables the recorded USB device address by setting ADDEN.
•on a hardware reset;
•when the USB macro is disabled (USBE = 0);
•when a USB reset is detected.
Wake-Up request can only be sent after a SUSP interrupt has been raised.
the actual address is still 0;
Section 30.7.1.6 on page 506
for further details.
for more details about DPRAM management.
Section 30.7.1.5.1 on
AT32UC3A
513