SC16C652IB48,151 NXP Semiconductors, SC16C652IB48,151 Datasheet - Page 26

• Manufacturer Part Number: SC16C652IB48,151
• Description: IC UART DUAL W/FIFO 48-LQFP
• Manufacturer: NXP Semiconductors

Specifications of SC16C652IB48,151

• Features: 2 Channels
• Number Of Channels: 2, DUART
• Fifo's: 32 Byte
• Voltage - Supply: 2.5V, 3.3V, 5V
• With Auto Flow Control: Yes
• With Irda Encoder/decoder: Yes
• With False Start Bit Detection: Yes
• With Modem Control: Yes
• With Cmos: Yes
• Mounting Type: Surface Mount
• Package / Case: 48-LQFP
• Transmitter And Receiver Fifo Counter: Yes
• Data Rate: 5Mbps
• Package Type: LQFP
• Operating Supply Voltage (max): 5.5V
• Mounting: Surface Mount
• Pin Count: 48
• Operating Temperature (min): -40C
• Operating Temperature (max): 85C
• Operating Temperature Classification: Industrial
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 568-3277; 935270032151; SC16C652IB48-S

Philips Semiconductors
9397 750 11634
Product data
Table 23:
Table 24:
[1]
Bit
5
4
3-0
Cont-3
0
1
0
1
X
X
X
1
0
1
When using a software flow control the Xon/Xoff characters cannot be used for data transfer.
Symbol
EFR[5]
EFR[4]
EFR[3-0] Cont-3-0 Tx, Rx control. Logic 0 or cleared is the default condition.
Cont-2
0
0
1
1
X
X
X
0
1
1
Enhanced Feature Register bits description
Software flow control functions
Description
Special Character Detect.
Enhanced function control bit. The content of IER[7-4], ISR[5-4], FCR[5-4],
and MCR[7-5] can be modified and latched. After modifying any bits in the
enhanced registers, EFR[4] can be set to a logic 0 to latch the new values.
This feature prevents existing software from altering or overwriting the
SC16C652 enhanced functions.
Combinations of software flow control can be selected by programming
these bits. See
Cont-1
X
X
X
X
0
1
0
1
1
1
Rev. 04 — 20 June 2003
Logic 0 = Special character detect disabled (normal default condition).
Logic 1 = Special character detect enabled. The SC16C652 compares
each incoming receive character with Xoff2 data. If a match exists, the
received data will be transferred to FIFO and ISR[4] will be set to
indicate detection of special character. Bit-0 in the X-registers
corresponds with the LSB bit for the receive character. When this feature
is enabled, the normal software flow control must be disabled (EFR[3-0]
must be set to a logic 0).
Logic 0 = disable/latch enhanced features. IER[7-4], ISR[5-4], FCR[5-4],
and MCR[7-5] are saved to retain the user settings, then IER[7-4]
ISR[5-4], FCR[5-4], and MCR[7-5] are set to a logic 0 to be compatible
with SC16C554 mode. (Normal default condition.)
Logic 1 = Enables the enhanced functions. When this bit is set to a
logic 1, all enhanced features of the SC16C652 are enabled and user
settings stored during a reset will be restored.
Dual UART with 32 bytes of transmit and receive FIFOs
Cont-0
X
X
X
X
0
0
1
1
1
1
Table
TX, RX software flow controls
No transmit flow control
Transmit Xon1/Xoff1
Transmit Xon2/Xoff2
Transmit Xon1 and Xon2/Xoff1 and Xoff2
No receive flow control
Receiver compares Xon1/Xoff1
Receiver compares Xon2/Xoff2
Transmit Xon1/Xoff1
Receiver compares Xon1 and Xon2, Xoff1 and Xoff2
Transmit Xon2/Xoff2
Receiver compares Xon1 and Xon2/Xoff1 and Xoff2
Transmit Xon1 and Xon2/Xoff1 and Xoff2
Receiver compares Xon1 and Xon2/Xoff1 and Xoff2
24.
[1]
…continued
© Koninklijke Philips Electronics N.V. 2003. All rights reserved.
SC16C652
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