SC16C652IB48,151 NXP Semiconductors, SC16C652IB48,151 Datasheet - Page 17

• Manufacturer Part Number: SC16C652IB48,151
• Description: IC UART DUAL W/FIFO 48-LQFP
• Manufacturer: NXP Semiconductors

Specifications of SC16C652IB48,151

• Features: 2 Channels
• Number Of Channels: 2, DUART
• Fifo's: 32 Byte
• Voltage - Supply: 2.5V, 3.3V, 5V
• With Auto Flow Control: Yes
• With Irda Encoder/decoder: Yes
• With False Start Bit Detection: Yes
• With Modem Control: Yes
• With Cmos: Yes
• Mounting Type: Surface Mount
• Package / Case: 48-LQFP
• Transmitter And Receiver Fifo Counter: Yes
• Data Rate: 5Mbps
• Package Type: LQFP
• Operating Supply Voltage (max): 5.5V
• Mounting: Surface Mount
• Pin Count: 48
• Operating Temperature (min): -40C
• Operating Temperature (max): 85C
• Operating Temperature Classification: Industrial
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 568-3277; 935270032151; SC16C652IB48-S

Philips Semiconductors
9397 750 11634
Product data
7.2.2 IER versus Receive/Transmit FIFO polled mode operation
7.3.1 DMA mode
7.3 FIFO Control Register (FCR)
When FCR[0] = logic 1, resetting IER[0-3] enables the SC16C652 in the FIFO polled
mode of operation. In this mode, interrupts are not generated and the user must poll
the LSR register for TX and/or RX data status. Since the receiver and transmitter
have separate bits in the LSR either or both can be used in the polled mode by
selecting respective transmit or receive control bit(s).
This register is used to enable the FIFOs, clear the FIFOs, set the receive FIFO
trigger levels, and select the DMA mode.
Mode 0 (FCR bit 3 = 0):
receive operation, and is similar to the 16C450 mode. Transmit Ready (TXRDY) will
go to a logic 0 whenever the FIFO (THR, if FIFO is not enabled) is empty. Receive
Ready (RXRDY) will go to a logic 0 whenever the Receive Holding Register (RHR) is
loaded with a character.
Mode 1 (FCR bit 3 = 1):
transmit interrupt is set when the transmit FIFO is below the programmed trigger
level. The receive interrupt is set when the receive FIFO fills to the programmed
trigger level. However, the FIFO continues to fill regardless of the programmed level
until the FIFO is full. RXRDY remains a logic 0 as long as the FIFO fill level is above
the programmed trigger level.
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LSR[0] will be a logic 1 as long as there is one byte in the receive FIFO.
LSR[1-4] will provide the type of receive errors, or a receive break, if encountered.
LSR[5] will indicate when the transmit FIFO is empty.
LSR[6] will indicate when both the transmit FIFO and transmit shift register are
empty.
LSR[7] will show if any FIFO data errors occurred.
Rev. 04 — 20 June 2003
Set and enable the interrupt for each single transmit or
Set and enable the interrupt in a block mode operation. The
Dual UART with 32 bytes of transmit and receive FIFOs
© Koninklijke Philips Electronics N.V. 2003. All rights reserved.
SC16C652
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