SC16C652IB48,151 NXP Semiconductors, SC16C652IB48,151 Datasheet - Page 13

IC UART DUAL W/FIFO 48-LQFP

SC16C652IB48,151

Manufacturer Part Number
SC16C652IB48,151
Description
IC UART DUAL W/FIFO 48-LQFP
Manufacturer
NXP Semiconductors
Datasheet

Specifications of SC16C652IB48,151

Features
2 Channels
Number Of Channels
2, DUART
Fifo's
32 Byte
Voltage - Supply
2.5V, 3.3V, 5V
With Auto Flow Control
Yes
With Irda Encoder/decoder
Yes
With False Start Bit Detection
Yes
With Modem Control
Yes
With Cmos
Yes
Mounting Type
Surface Mount
Package / Case
48-LQFP
Transmitter And Receiver Fifo Counter
Yes
Data Rate
5Mbps
Package Type
LQFP
Operating Supply Voltage (max)
5.5V
Mounting
Surface Mount
Pin Count
48
Operating Temperature (min)
-40C
Operating Temperature (max)
85C
Operating Temperature Classification
Industrial
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
568-3277
935270032151
SC16C652IB48-S

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
SC16C652IB48,151
Manufacturer:
NXP Semiconductors
Quantity:
10 000
Philips Semiconductors
9397 750 11634
Product data
Fig 4. Internal loop-back mode diagram.
RXRDYA, RXRDYB
TXRDYA, TXRDYB
INTA, INTB
CSA, CSB
RESET
D0–D7
A0–A2
IOW
IOR
SC16C652
CONTROL LOGIC
INTERRUPT
REGISTER
DATA BUS
CONTROL
SELECT
their normal modem control inputs pins, and instead are connected internally to RTS,
DTR, MCR[3] (OP2) and MCR[2] (OP1). Loop-back test data is entered into the
transmit holding register via the user data bus interface, D0-D7. The transmit UART
serializes the data and passes the serial data to the receive UART via the internal
loop-back connection. The receive UART converts the serial data back into parallel
data that is then made available at the user data interface D0-D7. The user optionally
compares the received data to the initial transmitted data for verifying error-free
operation of the UART TX/RX circuits.
In this mode, the receiver and transmitter interrupts are fully operational. The Modem
Control Interrupts are also operational.
LOGIC
LOGIC
AND
Rev. 04 — 20 June 2003
Dual UART with 32 bytes of transmit and receive FIFOs
XTAL1
GENERATOR
CLOCK AND
BAUD RATE
TRANSMIT
REGISTER
REGISTER
RECEIVE
FIFO
FIFO
XTAL2
TRANSMIT
REGISTER
REGISTER
RECEIVE
CONTROL
SHIFT
SHIFT
MODEM
LOGIC
© Koninklijke Philips Electronics N.V. 2003. All rights reserved.
MCR[4] = 1
002aaa350
SC16C652
TXA, TXB
RXA, RXB
RTSA, RTSB
CTSA, CTSB
DTRA, DTRB
DSRA, DSRB
(OP1A, OP1B)
RIA, RIB
(OP2A, OP2B)
CDA, CDB
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