SC16C652IB48,151 NXP Semiconductors, SC16C652IB48,151 Datasheet - Page 21

• Manufacturer Part Number: SC16C652IB48,151
• Description: IC UART DUAL W/FIFO 48-LQFP
• Manufacturer: NXP Semiconductors

Specifications of SC16C652IB48,151

• Features: 2 Channels
• Number Of Channels: 2, DUART
• Fifo's: 32 Byte
• Voltage - Supply: 2.5V, 3.3V, 5V
• With Auto Flow Control: Yes
• With Irda Encoder/decoder: Yes
• With False Start Bit Detection: Yes
• With Modem Control: Yes
• With Cmos: Yes
• Mounting Type: Surface Mount
• Package / Case: 48-LQFP
• Transmitter And Receiver Fifo Counter: Yes
• Data Rate: 5Mbps
• Package Type: LQFP
• Operating Supply Voltage (max): 5.5V
• Mounting: Surface Mount
• Pin Count: 48
• Operating Temperature (min): -40C
• Operating Temperature (max): 85C
• Operating Temperature Classification: Industrial
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 568-3277; 935270032151; SC16C652IB48-S

Philips Semiconductors
9397 750 11634
Product data
7.5 Line Control Register (LCR)
The Line Control Register is used to specify the asynchronous data communication
format. The word length, the number of stop bits, and the parity are selected by
writing the appropriate bits in this register.
Table 16:
Table 17:
Table 18:
Table 19:
Bit
7
6
5-3
2
1-0
LCR[5]
X
X
0
0
1
LCR[2]
0
1
1
LCR[1]
0
0
1
1
Line Control Register bits description
LCR[5-3] parity selection
LCR[2] stop bit length
LCR[1-0] word length
LCR[4]
X
0
1
0
1
Word length
5, 6, 7, 8
5
6, 7, 8
LCR[0]
0
1
0
1
Symbol
LCR[7]
LCR[6]
LCR[5-3]
LCR[2]
LCR[1-0]
Rev. 04 — 20 June 2003
LCR[3]
0
1
1
1
1
Word length
5
6
7
8
Description
Divisor latch enable. The internal baud rate counter latch and
Enhance Feature mode enable.
Set break. When enabled, the Break control bit causes a break
condition to be transmitted (the TX output is forced to a logic 0
state). This condition exists until disabled by setting LCR[6] to a
logic 0.
Programs the parity conditions (see
Stop bits. The length of stop bit is specified by this bit in
conjunction with the programmed word length (see
Word length bits 1, 0. These two bits specify the word length to be
transmitted or received (see
Dual UART with 32 bytes of transmit and receive FIFOs
Logic 0 = Divisor latch disabled (normal default condition).
Logic 1 = Divisor latch enabled.
Logic 0 = no TX break condition (normal default condition)
Logic 1 = forces the transmitter output (TX) to a logic 0 for
alerting the remote receiver to a line break condition.
Logic 0 or cleared = default condition.
Logic 0 or cleared = default condition.
Stop bit length (bit times)
1
1-
2
1
2
Parity selection
no parity
ODD parity
EVEN parity
forced parity ‘1’
forced parity ‘0’
Table
© Koninklijke Philips Electronics N.V. 2003. All rights reserved.
19).
Table
17).
SC16C652
Table
18).
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