SC16C652IB48,151 NXP Semiconductors, SC16C652IB48,151 Datasheet - Page 25

• Manufacturer Part Number: SC16C652IB48,151
• Description: IC UART DUAL W/FIFO 48-LQFP
• Manufacturer: NXP Semiconductors

Specifications of SC16C652IB48,151

• Features: 2 Channels
• Number Of Channels: 2, DUART
• Fifo's: 32 Byte
• Voltage - Supply: 2.5V, 3.3V, 5V
• With Auto Flow Control: Yes
• With Irda Encoder/decoder: Yes
• With False Start Bit Detection: Yes
• With Modem Control: Yes
• With Cmos: Yes
• Mounting Type: Surface Mount
• Package / Case: 48-LQFP
• Transmitter And Receiver Fifo Counter: Yes
• Data Rate: 5Mbps
• Package Type: LQFP
• Operating Supply Voltage (max): 5.5V
• Mounting: Surface Mount
• Pin Count: 48
• Operating Temperature (min): -40C
• Operating Temperature (max): 85C
• Operating Temperature Classification: Industrial
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 568-3277; 935270032151; SC16C652IB48-S

Philips Semiconductors
9397 750 11634
Product data
7.10 Enhanced Feature Register (EFR)
7.9 Scratchpad Register (SPR)
Table 22:
[1]
The SC16C652 provides a temporary data register to store 8 bits of user information.
Enhanced features are enabled or disabled using this register.
Bits 0 through 4 provide single or dual character software flow control selection.
When the Xon1 and Xon2 and/or Xoff1 and Xoff2 modes are selected, the double
8-bit words are concatenated into two sequential numbers.
Table 23:
Bit
1
0
Bit
7
6
Whenever any MSR bit 0-3 is set to logic 1, a Modem Status Interrupt will be generated.
Symbol
EFR[7]
EFR[6]
Modem Status Register bits description
Enhanced Feature Register bits description
Symbol
MSR[1]
MSR[0]
Description
Automatic CTS flow control.
Automatic RTS flow control. Automatic RTS may be used for hardware flow
control by enabling EFR[6]. When Auto-RTS is selected, an interrupt will
be generated when the receive FIFO is filled to the programmed trigger
level and RTS will go to a logic 1 at the next trigger level. RTS will return to
a logic 0 when data is unloaded below the next lower trigger level
(programmed trigger level 1). The state of this register bit changes with the
status of the hardware flow control. RTS functions normally when
hardware flow control is disabled.
Rev. 04 — 20 June 2003
Logic 0 = Automatic CTS flow control is disabled (normal default
condition).
Logic 1 = Enable Automatic CTS flow control. Transmission will stop
when CTS goes to a logical 1. Transmission will resume when the CTS
pin returns to a logical 0.
0 = Automatic RTS flow control is disabled (normal default condition).
1 = Enable Automatic RTS flow control.
Description
DSR
CTS
Dual UART with 32 bytes of transmit and receive FIFOs
Logic 0 = No DSR change (normal default condition).
Logic 1 = The DSR input to the SC16C652 has changed state
since the last time it was read. A modem Status Interrupt will be
generated.
Logic 0 = No CTS change (normal default condition).
Logic 1 = The CTS input to the
since the last time it was read. A modem Status Interrupt will be
generated.
[1]
[1]
…continued
© Koninklijke Philips Electronics N.V. 2003. All rights reserved.
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