SC28L92A1BS,551 NXP Semiconductors, SC28L92A1BS,551 Datasheet - Page 58
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SC28L92A1BS,551
Manufacturer Part Number
SC28L92A1BS,551
Description
IC UART DUAL W/FIFO 44PQFP
Manufacturer
NXP Semiconductors
Series
IMPACTr
Datasheet
1.SC28L92A1B557.pdf
(73 pages)
Specifications of SC28L92A1BS,551
Features
False-start Bit Detection
Number Of Channels
2, DUART
Fifo's
16 Byte
Voltage - Supply
3.3V, 5V
With Auto Flow Control
Yes
With False Start Bit Detection
Yes
With Modem Control
Yes
With Cmos
Yes
Mounting Type
Surface Mount
Package / Case
48-VQFN Exposed Pad, 48-HVQFN, 48-SQFN, 48-DHVQFN
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
935281063551
SC28L92A1BS-S
SC28L92A1BS-S
SC28L92A1BS-S
SC28L92A1BS-S
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
SC28L92A1BS,551
Manufacturer:
NXP Semiconductors
Quantity:
10 000
NXP Semiconductors
[7]
11. Timing diagrams
SC28L92_7
Product data sheet
Minimum DACKN time is ((t
cycles, the 80xxx bus timing may be used while in the 68xxx mode. It is not necessary to wait for DACKN to insure the proper operation
of the SC26C92. In all cases the data will be written to the SC28L92 on the falling edge of DACKN or the rise of CEN. The fall of CEN
initializes the bus cycle. The rise of CEN ends the bus cycle. DACKN LOW or CEN HIGH completes the write cycle.
Fig 10. Reset timing
Fig 11. Bus timing (80xxx mode)
DCR
RESET
a. 80xxx mode
or t
D0 to D7
D0 to D7
A0 to A3
DCW
(write)
(read)
WDN
RDN
CEN
) t
CSC
+ 2 X1 edges + rise time over 5 ns). Two X1 edges is 273 ns at 3.6864 MHz. For faster bus
float
Rev. 07 — 19 December 2007
3.3 V/5.0 V Dual Universal Asynchronous Receiver/Transmitter
t
t
AS
CS
t
RES
not valid
t
AH
001aae303
t
DD
t
RW
t
DS
valid
valid
RESETN
b. 68xxx mode
t
CS
t
DF
t
DH
t
t
RWD
RWD
float
t
RES
SC28L92
© NXP B.V. 2007. All rights reserved.
001aae305
001aae304
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