PSB 21373 H V1.1 Infineon Technologies, PSB 21373 H V1.1 Datasheet - Page 86

• Manufacturer Part Number: PSB 21373 H V1.1
• Description: IC SPEECH AND VOICE MQFP-44
• Manufacturer: Infineon Technologies
• Series: SCOUT™r

Specifications of PSB 21373 H V1.1

• Function: CODEC
• Interface: IOM-2, SCI
• Number Of Circuits: 1
• Voltage - Supply: 5V
• Current - Supply: 97.5mA
• Mounting Type: Surface Mount
• Package / Case: 44-BQFP
• Includes: Activation and Deactivation, Channel Handler, DTMF / Tone / Ringing Generator, HDLC Controller, Speakerphone, Voice Monitoring
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Power (watts): -
• Operating Temperature: -
• Other names: PSB21373HV1.1XT; PSB21373HV11XT; SP000007602

3.1.1
Characteristics:
All frames with valid addresses are accepted and the bytes following the address are
transferred to the P via RFIFO.
3.1.2
Characteristics:
Every received frame is stored in RFIFO (first byte after opening flag to CRC field).
3.1.3
Characteristics:
A comparison is performed on the first byte after the opening flag with SAP1, SAP2 and
“group” SAPI (FE
3.1.4
Characteristics:
A comparison is performed only on the second byte after the opening flag, with TEI1,
TEI2 and group TEI (FF
3.1.5
Characteristics:
In extended transparent mode fully transparent data transmission/reception without
HDLC framing is performed i.e. without FLAG generation/recognition, CRC generation/
check, bit stuffing mechanism. This allows user specific protocol variations.
Also refer to chapter 3.5.
3.2
3.2.1
3.2.1.1
The 64-byte cyclic RFIFO buffer has variable FIFO block sizes (thresholds) of 4, 8, 16 or
32 bytes which can be selected by setting the corresponding RFBS bits in the EXMR
register. The variable block size allows an optimized HDLC processing concerning frame
length, I/O throughput and interrupt load.
The transfer protocol between HDLC FIFO and microcontroller is block orientated with
Data Sheet
Non-Auto Mode (MDS2-0 = ’01x’)
Transparent Mode 0 (MDS2-0 = ’110’).
Transparent Mode 1 (MDS2-0 = ’111’).
Transparent Mode 2 (MDS2-0 = ’101’).
Extended Transparent Mode (MDS2-0 = ’100’).
Data Reception
Structure and Control of the Receive FIFO
General Description
H
/FC
Full address recognition with one-byte (MDS = ’010’) or
two-byte (MDS = ’011’) address comparison
no address recognition
SAPI recognition
TEI recognition
fully transparent
H
). In the case of a match, all following bytes are stored in RFIFO.
H
). In case of a match the rest of the frame is stored in the RFIFO.
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PSB 21373
2002-05-13