PSB 21373 H V1.1 Infineon Technologies, PSB 21373 H V1.1 Datasheet - Page 160
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PSB 21373 H V1.1
Manufacturer Part Number
PSB 21373 H V1.1
Description
IC SPEECH AND VOICE MQFP-44
Manufacturer
Infineon Technologies
Series
SCOUT™r
Datasheet
1.PSB_21373_H_V1.1.pdf
(242 pages)
Specifications of PSB 21373 H V1.1
Function
CODEC
Interface
IOM-2, SCI
Number Of Circuits
1
Voltage - Supply
5V
Current - Supply
97.5mA
Mounting Type
Surface Mount
Package / Case
44-BQFP
Includes
Activation and Deactivation, Channel Handler, DTMF / Tone / Ringing Generator, HDLC Controller, Speakerphone, Voice Monitoring
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Power (watts)
-
Operating Temperature
-
Other names
PSB21373HV1.1XT
PSB21373HV11XT
SP000007602
PSB21373HV11XT
SP000007602
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6.1
The internal reset sources C/I code change, EAW and Watchdog can be output at the
low active reset pin RSTO/SDS2. The selection of these reset sources can be done with
the RSS2,1 bits in the MODE1 register according table 23.
If RSS2,1 =’01’ the RSTO/SDS2 pin has SDS2 functionality and a serial data strobe
signal (see chapter 2.2.3) is output at the RSTO/SDS2 pin. In this case no reset except
the hardware reset is output at RSTO/SDS2. The internal reset sources set the MODE1
register to its default value.
Table 23
Reset Source Selection
RSS2
Bit 1
0
0
1
1
• C/I Code Change (Exchange Awake) A change in the downstream C/I channel (C/
• EAW (Subscriber Awake)
• Watchdog Timer
Data Sheet
I0) generates a reset pulse of 125µs
A low pulse of at least 65 as pulse width on the EAW input starts the oscillator from
the power down state and generates a reset pulse of 125 µs
After the selection of the watchdog timer (RSS =’11’) an internal timer is reset and
started. During every time period of 128 ms the microcontroller has to program the
WTC1- and WTC2 bits in the following sequence to reset and restart the watchdog
timer:
If not, the timer expires and a WOV-interrupt (ISTA Register) together with a reset
pulse of 125 µs is generated.
If the watchdog timer is enabled (RSS = ’11’) the RSS bits can only be changed by a
hardware reset.
RSS1
Bit 0
0
1
0
1
Reset Source Selection
1.
2.
C/I Code
Change
--
--
x
--
WTC1
1
0
EAW
--
--
x
--
t
WTC2
0
1
160
250µs.
Watchdog
Timer
--
--
--
x
t
250 µs.
SDS2
Functionality
--
x
--
--
PSB 21373
2002-05-13
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