PSB 21373 H V1.1 Infineon Technologies, PSB 21373 H V1.1 Datasheet - Page 40

• Manufacturer Part Number: PSB 21373 H V1.1
• Description: IC SPEECH AND VOICE MQFP-44
• Manufacturer: Infineon Technologies
• Series: SCOUT™r

Specifications of PSB 21373 H V1.1

• Function: CODEC
• Interface: IOM-2, SCI
• Number Of Circuits: 1
• Voltage - Supply: 5V
• Current - Supply: 97.5mA
• Mounting Type: Surface Mount
• Package / Case: 44-BQFP
• Includes: Activation and Deactivation, Channel Handler, DTMF / Tone / Ringing Generator, HDLC Controller, Speakerphone, Voice Monitoring
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Power (watts): -
• Operating Temperature: -
• Other names: PSB21373HV1.1XT; PSB21373HV11XT; SP000007602

2.2.2.1.4
While looping, shifting and switching the data can be accessed by the controller between
the synchronous transfer interrupt (STI) and the status overflow interrupt (STOV).
The microcontroller access to the CDAxy registers can be synchronized by means of
four programmable synchronous transfer interrupts (STIxy) and synchronous transfer
overflow interrupts (STOVxy) in the STI register.
Depending on the DPS bit in the corresponding CDA_TSDPxy register the STIxy is
generated two (for DPS=’0’) or one (for DPS=’1’) BCL clock after the selected time slot
(CDA_TSDPxy.TSS). One BCL clock is equivalent to two DCL clocks.
A non masked synchronous transfer overflow (STOVx
appropriate STIx
bit ACKx
clocks (for DPS=’1’) before the time slot which is selected for the appropriate STOVx
If STIx
example a), c) and d) of figure 17).
If STIx
STIxy (see example b) and d) of figure 17).
Setting the corresponding bits in the MSTI (Mask Synchronous Transfer Interrupts)
register masks the STIxy and the STOVxy interrupt. The interrupt structure of the
synchronous transfer is shown in figure 16. Examples of the described synchronous
transfer interrupt controlling are illustrated in Figure 17. A read to the STI register clears
the STIxy and STOVxy interrupts.
.
Figure 16
Interrupt Structure of the Synchronous Data Transfer
Data Sheet
TRAN
HDLC
WOV
MOS
MASK
TIN
CIC
ST
INT
1
1
y
y
1
1
1
y
is masked but STOVx
and STOVx
1
Synchronous Transfer
in the ASTI register is set to ’1’ one BCL clock (for DPS=’0’) or zero BCL
1
y
TRAN
HDLC
MOS
WOV
1
ISTA
CIC
TIN
ST
is not acknowledged in time. The STIx
1
y
1
are not masked STOVx
1
y
1
is not masked, STOVx
STOV21
STOV20
STOV11
STOV10
MSTI
STI20
STI11
STI10
STI21
40
1
y
1
0
is only related to STIx
STOV10
STOV20
STOV11
STOV21
y
STI21
STI20
STI11
STI10
0
0
) interrupt is generated if the
1
STI
y
y
0
1
is related to each enabled
is acknowledged in time if
ACK10
ACK11
ACK21
ACK20
ASTI
PSB 21373
2002-05-13
1
y
1
(see
0
y
0
.