DS3171N+ Maxim Integrated Products, DS3171N+ Datasheet - Page 83

• Manufacturer Part Number: DS3171N+
• Description: TXRX SGL DS3/E3 400PBGA
• Manufacturer: Maxim Integrated Products

Specifications of DS3171N+

• Function: Single-Chip Transceiver
• Interface: DS3, E3
• Number Of Circuits: 1
• Voltage - Supply: 3.135 V ~ 3.465 V
• Current - Supply: 273mA
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 400-BGA
• Includes: DS3 Framers, E3 Framers, HDLC Controller, On-Chip BERTs
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Power (watts): -
• Other names: 90-31710+N00

P-bit parity errors are determined by calculating the parity of the current DS3 frame (payload bits only), and
comparing the calculated parity to the P-bits (P
match P
C-bit parity errors (C-bit format only) are determined by calculating the parity of the current DS3 frame (payload bits
only), and comparing the calculated parity to the C-bits in subframe three (C
If the calculated parity does not match C
FEBE errors (C-bit format only) are determined by the C-bits in subframe four (C
indicates no error and any other value indicates an error.
The receive alarm indication (RAI) bit will be set high in the transmitter when one or more of the indicated alarm
conditions is present, and low when all of the indicated alarm conditions are absent. Setting the receive alarm
indication on LOS, SEF, LOF, or AIS is individually programmable (on or off).
The Application Identification Channel (AIC) is stored in a register bit. It is determined from the C
set to one (C-bit format) if the C
format) if the C
must not change when an LOS, OOF, or AIS condition is present.
A FEBE is transmitted by default upon reception of a DS3 frame in which a C-bit parity error or a framing error is
detected and counted.
10.6.5 C-Bit DS3 Framer/Formatter
10.6.5.1 Transmit C-bit DS3 Frame Processor
The C-bit DS3 frame format is shown in
DS3 Frame.
Table 10-27. C-Bit DS3 Frame Overhead Bit Definitions
Bit
X
P
M
F
C
C
C
C
C
C
C
C
C
XY
1
1
11
12
13
21
31
41
51
61
71
1
, X
, P
, M
, C
, C
, C
, C
, C
, C
2
2
2
22
32
42
52
62
72
, and M
, and C
, and C
, and C
, and C
, and C
, and C
1
or P
2
3
, a single P-bit parity error is declared.
23
33
43
53
63
73
11
bit is set to zero in four of the last thirty-one consecutive multiframes. Note: The stored AIC bit
Definition
Remote Defect Indication
(RDI)
Parity Bits
Multiframe Alignment Bits
Subframe Alignment Bits
Application Identification
Channel (AIC)
Reserved
Far-End Alarm and Control
(FEAC) signal
Unused
C-bit parity bits
Far-End Block Error (FEBE)
bits
Path Maintenance Data Link
(or HDLC) bits
Unused
Unused
11
bit is set to one in thirty-one consecutive multiframes. The AIC is set to zero (M23
31
Figure
, C
32
, or C
10-14.
1
and P
33
, a single C-bit parity error is declared.
Table 10-27
2
83
) in the next DS3 frame. If the calculated parity does not
shows the function of each overhead bit in the
31
, C
32
, and C
41
, C
42
, and C
33
) in the next DS3 frame.
43
). A value of 111
11
bit. The AIC is