DS3171N+ Maxim Integrated Products, DS3171N+ Datasheet - Page 54

• Manufacturer Part Number: DS3171N+
• Description: TXRX SGL DS3/E3 400PBGA
• Manufacturer: Maxim Integrated Products

Specifications of DS3171N+

• Function: Single-Chip Transceiver
• Interface: DS3, E3
• Number Of Circuits: 1
• Voltage - Supply: 3.135 V ~ 3.465 V
• Current - Supply: 273mA
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 400-BGA
• Includes: DS3 Framers, E3 Framers, HDLC Controller, On-Chip BERTs
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Power (watts): -
• Other names: 90-31710+N00

10.2.1.2.4 LIU Disabled - CLAD Timing Enabled – no LB
In this mode, the RLCLKn pins source the clock for the receive logic and one of the CLAD clocks sources the clock
for the transmit logic.
10.2.2 Sources of Clock Output Pin Signals
The clock output pins can be sourced from many clock sources. The clock sources are the transmit input clocks
pins (TCLKIn), the receive clock input pins (RLCLKn), the recovered clock in the receive LIUs, and the clock
signals in the clock rate adapter circuit (CLAD). The default clock source for the receive logic is the RLCLKn pin if
the LIU is disabled; otherwise the default clock is sourced from the RX LIU clock when the RX LIU is enabled. The
default clock source for the transmit logic is the CLAD clocks.
The LIU is enabled based on the line mode bits(LM[2:0]) (See
and CLADC are located in the port configuration registers. LIUEN is not a register bit; it is a variable based on the
line mode bits.
Table 10-1. LIU Enable Table
Table 10-2
configured. Putting the device in loopback will typically mux in a different clock than the normal clock source.
Table 10-2. All Possible Clock Sources Based on Mode and Loopback
Table 10-3
Loop Timed
LM[2:0]
Normal
Normal
Normal
Normal
Normal
MODE
1XX
000
001
010
011
identifies the source of the output signal TLCLKn based on certain variables and register bits.
identifies the framer clock source and the line clock source depending on the mode that the device is
Table 10-1
LLB and DLB
LOOPBACK
LIUEN
0
1
1
1
0
None
DLB
PLB
Any
LLB
decodes the LM bits for LiUEN selection.
LIU Status
Disabled
Disabled
Enabled
Enabled
Enabled
Rx FRAMER
Same as Tx
Same as Tx
RLCLKn or
RLCLKn or
RLCLKn or
RLCLKn or
SOURCE
CLOCK
RXLIU
RXLIU
RXLIU
RXLIU
Tx FRAMER
Same as Rx
Same as Rx
TCLKIn or
TCLKIn or
TCLKIn or
TCLKIn or
SOURCE
CLOCK
CLAD
CLAD
CLAD
CLAD
54
Table
Same as Rx
Same as Rx
Same as Rx
Same as Tx
Same as Tx
RLCLKn or
10-26). The bits LM[2:0], LBM[2:0], LOOPT
SOURCE
Tx LINE
CLOCK
RXLIUn