DS3171N+ Maxim Integrated Products, DS3171N+ Datasheet - Page 233

• Manufacturer Part Number: DS3171N+
• Description: TXRX SGL DS3/E3 400PBGA
• Manufacturer: Maxim Integrated Products

Specifications of DS3171N+

• Function: Single-Chip Transceiver
• Interface: DS3, E3
• Number Of Circuits: 1
• Voltage - Supply: 3.135 V ~ 3.465 V
• Current - Supply: 273mA
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 400-BGA
• Includes: DS3 Framers, E3 Framers, HDLC Controller, On-Chip BERTs
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Power (watts): -
• Other names: 90-31710+N00

18.8 JTAG Interface AC Characteristics
All AC timing characteristics are specified with a 50pF capacitive load on JTDO pin and 25pF capacitive load on all
other digital output pins, V
generic timing definitions shown
interface.
Table 18-13. JTAG Interface Timing
(V
Note 1:
Note 2:
Note 3:
Any digital output
Any digital output
Any digital output
Any digital output
Any digital output
Any digital output
DD
JTMS and JTDI
JTMS and JTDI
= 3.3V ±5%, T
NAME(S)
SIGNAL
JTCLK
JTCLK
JTCLK
JTDO
JTDO
JTDO
Change during Update-DR state.
Change during Update-IR state to or from EXTEST mode.
Change during Update-IR state to or from HIZ mode.
j
= -40°C to +125°C.)
SYMBOL
f1
t2
t3
t5
t6
t7
t8
t9
t7
t8
t8
t7
t9
t9
IH
= 2.4V and V
Figure
Clock Frequency (1/t1)
Clock High or Low Period
Rise/Fall Times
Hold Time from JTCLK Rising Edge
Setup Time to JTCLK Rising Edge
Delay from JTCLK Falling Edge
Delay out of HiZ from JTCLK Falling Edge
Delay to HiZ from JTCLK Falling Edge
Delay from JTCLK Falling Edge
Delay from JTCLK Rising Edge
Delay out of HiZ from JTCLK Falling Edge
Delay into HiZ from JTCLK Falling Edge
Delay out of HiZ from JTCLK Rising Edge
Delay into HiZ from JTCLK Rising Edge
18-1,
IL
= 0.8. The voltage threshold for all timing measurements is V
Figure
DESCRIPTION
18-2,
233
Figure
18-3,
Figure
MIN TYP
20
10
10
0
0
0
0
0
0
0
0
0
0
18-5, and
Figure 18-6
MAX
10
20
20
20
20
20
20
20
20
20
5
UNITS NOTES
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
apply to this
DD
/2. The
2, 3
2, 3
1
1
2
1