DS3171N+ Maxim Integrated Products, DS3171N+ Datasheet - Page 165

• Manufacturer Part Number: DS3171N+
• Description: TXRX SGL DS3/E3 400PBGA
• Manufacturer: Maxim Integrated Products

Specifications of DS3171N+

• Function: Single-Chip Transceiver
• Interface: DS3, E3
• Number Of Circuits: 1
• Voltage - Supply: 3.135 V ~ 3.465 V
• Current - Supply: 273mA
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 400-BGA
• Includes: DS3 Framers, E3 Framers, HDLC Controller, On-Chip BERTs
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Power (watts): -
• Other names: 90-31710+N00

12.7 FEAC Controller
12.7.1 FEAC Transmit Side Register Map
The transmit side utilizes five registers.
Table 12-19. FEAC Transmit Side Register Map
12.7.1.1 Register Bit Descriptions
Register Name:
Register Description:
Register Address:
Bit #
Name
Default
Bit #
Name
Default
Bit 2: Transmit FEAC Codeword Load (TFCL) – A 0 to 1 transition on this bit loads the transmit FEAC processor
mode select bits (TFS[1:0]), and transmit FEAC codes (TFCA[5:0] and TFCB[5:0]). Note: Whenever a FEAC
codeword is loaded, any current FEAC codeword transmission in progress will be immediately halted, and the new
FEAC codeword transmission will be started based on the new values for TFS[1:0], TFCA[5:0], and TFCB[5:0]..
Bits 1 to 0: Transmit FEAC Codeword Select (TFS[1:0]) – These two bits control the transmit FEAC processor
mode. The TFCL bit loads the mode set by this bit.
(0,2,4,6)CCh
(0,2,4,6)CAh
(0,2,4,6)CEh
(0,2,4,6)C0h FEAC.TCR
(0,2,4,6)C2h FEAC.TFDR
(0,2,4,6)C4h FEAC.TSR
(0,2,4,6)C6h FEAC.TSRL
(0,2,4,6)C8h FEAC.TSRIE
Address
00 = Idle (all ones)
01 = single code (send code TFCA ten times and send all ones)
10 = dual code (send code TFCA ten times, send code TFCB ten times, and send all ones)
11 = continuous code (send code TFCA continuously)
15
--
--
0
7
0
Register
14
--
--
0
6
0
--
--
--
FEAC.TCR
FEAC Transmit Control Register
(0,2,4,6)C0h
13
--
--
0
5
0
FEAC Transmit Control Register
FEAC Transmit Data Register
FEAC Transmit Status Register
FEAC Transmit Status Register Latched
FEAC Transmit Status Register Interrupt Enable
Unused
Unused
Unused
Register Description
12
--
--
0
0
4
165
11
--
--
1
3
0
TFCL
10
--
0
2
0
TFS1
--
9
0
1
0
TFS0
--
8
0
0
0