DS3171N+ Maxim Integrated Products, DS3171N+ Datasheet - Page 198

• Manufacturer Part Number: DS3171N+
• Description: TXRX SGL DS3/E3 400PBGA
• Manufacturer: Maxim Integrated Products

Specifications of DS3171N+

• Function: Single-Chip Transceiver
• Interface: DS3, E3
• Number Of Circuits: 1
• Voltage - Supply: 3.135 V ~ 3.465 V
• Current - Supply: 273mA
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 400-BGA
• Includes: DS3 Framers, E3 Framers, HDLC Controller, On-Chip BERTs
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Power (watts): -
• Other names: 90-31710+N00

(1,3,5,7)20h
(1,3,5,7)22h
(1,3,5,7)24h
(1,3,5,7)26h
(1,3,5,7)28h
(1,3,5,7)2Ah
(1,3,5,7)2Ch
(1,3,5,7)2Eh
(1,3,5,7)30h
(1,3,5,7)32h
(1,3,5,7)34h
(1,3,5,7)36h
(1,3,5,7)38h
(1,3,5,7)3Ah
(1,3,5,7)3Ch
(1,3,5,7)3Eh
12.9.6 Receive G.832 E3 Register Map
The receive G.832 E3 utilizes thirteen registers.
Table 12-28. Receive G.832 E3 Framer Register Map
Address
12.9.6.1 Register Bit Descriptions
Register Name:
Register Description:
Register Address:
Bit #
Name
Default
Bit #
Name
Default
Bit 14: Parity Error Count (PEC) – When 0, BIP-8 block errors (EM byte) are detected (no more than one per
frame). When 1, BIP-8-bit errors are detected (up to 8 per frame).
Bit 13: Receive HDLC Data Link Source (DLS) – When 0, the receive HDLC data link will be sourced from the
GC byte. When 1, the receive HDLC data link will be sourced from the NR byte.
Bit 12: Manual Downstream AIS Insertion (MDAISI) – When 0, manual downstream AIS insertion is disabled.
When 1, manual downstream AIS insertion is enabled.
Bit 11: Automatic Downstream AIS Disable (AAISD) – When 0, the presence of an LOS, OOF, or AIS condition
will cause downstream AIS to be inserted. When 1, the presence of an LOS, OOF, or AIS condition will not cause
downstream AIS to be inserted.
Bit 10: Error Count Control (ECC) – When 0, framing errors, parity errors, and REI errors will not be counted if an
OOF or AIS condition is present. Parity errors and REI errors will also not be counted during the E3 frame in which
Reserved
RDILE
E3G832.RCR
E3G832.RMACR
E3G832.RSR1
E3G832.RSR2
E3G832.RSRL1
E3G832.RSRL2
E3G832.RSRIE1
E3G832.RSRIE2
E3G832.RMABR
E3G832.RNGBR
E3G832.RFECR
E3G832.RPECR
E3G832.RFBER
15
0
7
0
Register
--
--
--
RDILD
PEC
14
0
6
0
E3G832.RCR
E3 G.832 Receive Control Register
(1,3,5,7)20h
E3 G.832 Receive Control Register
E3 G.832 Receive MA Byte Control Register
E3 G.832 Receive Status Register #1
E3 G.832 Receive Status Register #2
E3 G.832 Receive Status Register Latched #1
E3 G.832 Receive Status Register Latched #2
E3 G.832 Receive Status Register Interrupt Enable #1
E3 G.832 Receive Status Register Interrupt Enable #2
E3 G.832 Receive MA Byte Register
E3 G.832 Receive NR and GC Byte Register
E3 G.832 Receive Framing Error Count Register
E3 G.832 Receive Parity Error Count Register
E3 G.832 Receive Remote Error Indication Count Register
Reserved
Unused
Unused
Register Description
RDIOD
DLS
13
0
5
0
MDAISI
RDIAD
12
0
0
4
198
ROMD
AAISD
11
0
3
0
ECC
LIP1
10
0
2
0
FECC1
LIP0
9
0
1
0
FRSYNC
FECC0
8
0
0
0