A3P125-QNG132 MICROSEMI, A3P125-QNG132 Datasheet - Page 9

• Manufacturer Part Number: A3P125-QNG132
• Manufacturer: MICROSEMI

Specifications of A3P125-QNG132

• Lead Free Status / Rohs Status: Compliant

Figure 1-1 • Automotive ProASIC3 Device Architecture Overview with Two I/O Banks (A3P060 and A3P125)
Advanced Architecture
The proprietary Automotive ProASIC3 architecture provides granularity comparable to standard-cell
ASICs. The Automotive ProASIC3 device consists of five distinct and programmable architectural
features
The FPGA core consists of a sea of VersaTiles. Each VersaTile can be configured as a three-input logic
function, a D-flip-flop (with or without enable), or a latch by programming the appropriate flash switch
interconnections. The versatility of the Automotive ProASIC3 core tile as either a three-input lookup table
(LUT) equivalent or a D-flip-flop/latch with enable allows for efficient use of the FPGA fabric. The
VersaTile capability is unique to the Actel ProASIC family of third-generation-architecture flash FPGAs.
VersaTiles are connected with any of the four levels of routing hierarchy. Flash switches are distributed
throughout the device to provide nonvolatile, reconfigurable interconnect programming. Maximum core
utilization is possible for virtually any design.
In addition, extensive on-chip programming circuitry allows for rapid, single-voltage (3.3 V) programming
of Automotive ProASIC3 devices via an IEEE 1532 JTAG interface.
•
•
•
•
•
Decryption
ISP AES
FPGA VersaTiles
Dedicated FlashROM
Dedicated SRAM memory
Extensive CCCs and PLLs
Advanced I/O structure
(Figure 1-1
and
Figure 1-2 on page
User Nonvolatile
FlashROM
Bank 0
Bank 1
R e v i s i o n 1
1-4):
Charge Pumps
Automotive ProASIC3 Flash Family FPGAs
RAM Block
4,608-Bit SRAM
or FIFO Block
CCC
I/Os
VersaTile
1 -3