A3P125-QNG132 MICROSEMI, A3P125-QNG132 Datasheet - Page 21

• Manufacturer Part Number: A3P125-QNG132
• Manufacturer: MICROSEMI

Specifications of A3P125-QNG132

• Lead Free Status / Rohs Status: Compliant

Table 2-11 • Different Components Contributing to Dynamic Power Consumption in ProASIC3 Devices
Parameter
P
P
P
P
P
P
P
P
P
P
P
P
P
P
*
AC1
AC2
AC3
AC4
AC5
AC6
AC7
AC8
AC9
AC10
AC11
AC12
AC13
AC14
For a different output load, drive strength, or slew rate, Actel recommends using the Actel power spreadsheet
calculator or SmartPower tool in Actel Libero
Clock contribution of a Global Rib
Clock contribution of a Global Spine
Clock contribution of a VersaTile row
Clock contribution of a VersaTile used as a sequential module
First contribution of a VersaTile used as a sequential module
Second contribution of a VersaTile used as a sequential module
Contribution of a VersaTile used as a combinatorial module
Average contribution of a routing net
Contribution of an I/O input pin (standard-dependent)
Contribution of an I/O output pin (standard-dependent)
Average contribution of a RAM block during a read operation
Average contribution of a RAM block during a write operation
Static PLL contribution
Dynamic contribution for PLL
Power Consumption of Various Internal Resources
Power Calculation Methodology
This section describes a simplified method to estimate power consumption of an application. For more
accurate and detailed power estimations, use the SmartPower tool in Actel Libero IDE software.
The power calculation methodology described below uses the following variables:
Methodology
Total Power Consumption—P
P
P
STAT
DYN
•
•
•
•
•
•
•
•
P
TOTAL
is the total dynamic power consumption.
is the total static power consumption.
The number of PLLs as well as the number and the frequency of each output clock generated
The number of combinatorial and sequential cells used in the design
The internal clock frequencies
The number and the standard of I/O pins used in the design
The number of RAM blocks used in the design
Toggle rates of I/O pins as well as VersaTiles—guidelines are provided in
page
Enable rates of output buffers—guidelines are provided for typical applications in
page
Read rate and write rate to the memory—guidelines are provided for typical applications in
Table 2-13 on page
design.
= P
2-11.
2-12.
STAT
+ P
DYN
Definition
2-12. The calculation should be repeated for each clock domain defined in the
®
Integrated Design Environment (IDE).
TOTAL
R e v i s i o n 1
A3P1000 A3P250 A3P125 A3P060
Automotive ProASIC3 Flash Family FPGAs
14.50
Device Specific Dynamic Power
2.48
See
See
Table 2-7
Table 2-7 on page
11.00
1.58
(µW/MHz)
page
2.55 mW
25.00
30.00
0.81
0.12
0.07
0.29
0.29
0.70
2.60
and
2-8.
Table 2-10 on
11.00
0.81
Table 2-12 on
Table 2-13 on
2-6.
9.30
0.81
2 -9