A3P125-QNG132 MICROSEMI, A3P125-QNG132 Datasheet - Page 88

• Manufacturer Part Number: A3P125-QNG132
• Manufacturer: MICROSEMI

Specifications of A3P125-QNG132

• Lead Free Status / Rohs Status: Compliant

Automotive ProASIC3 DC and Switching Characteristics
Table 2-108 • A3P060 Global Resource
Table 2-109 • A3P060 Global Resource
2- 76
Parameter
t
t
t
t
t
F
Notes:
1. Value reflects minimum load. The delay is measured from the CCC output to the clock pin of a sequential element,
2. Value reflects maximum load. The delay is measured on the clock pin of the farthest sequential element, located in a fully
3. For specific junction temperature and voltage supply levels, refer to
Parameter
t
t
t
t
t
F
Notes:
1. Value reflects minimum load. The delay is measured from the CCC output to the clock pin of a sequential element,
2. Value reflects maximum load. The delay is measured on the clock pin of the farthest sequential element, located in a fully
3. For specific junction temperature and voltage supply levels, refer to
RCKL
RCKH
RCKMPWH
RCKMPWL
RCKSW
RCKL
RCKH
RCKMPWH
RCKMPWL
RCKSW
RMAX
RMAX
located in a lightly loaded row (single element is connected to the global net).
loaded row (all available flip-flops are connected to the global net in the row).
located in a lightly loaded row (single element is connected to the global net).
loaded row (all available flip-flops are connected to the global net in the row).
Global Tree Timing Characteristics
Global clock delays include the central rib delay, the spine delay, and the row delay. Delays do not
include I/O input buffer clock delays, as these are I/O standard–dependent, and the clock may be driven
and conditioned internally by the CCC module. For more details on clock conditioning capabilities, refer
to the
page 2-98
maximum delays are measured with minimum and maximum loading.
Timing Characteristics
Commercial-Case Conditions: T
Commercial-Case Conditions: T
Input Low Delay for Global Clock
Input High Delay for Global Clock
Minimum Pulse Width High for Global Clock
Minimum Pulse Width Low for Global Clock
Maximum Skew for Global Clock
Maximum Frequency for Global Clock
Input Low Delay for Global Clock
Input High Delay for Global Clock
Minimum Pulse Width High for Global Clock
Minimum Pulse Width Low for Global Clock
Maximum Skew for Global Clock
Maximum Frequency for Global Clock
"Clock Conditioning Circuits" section on page
present minimum and maximum global clock delays within each device. Minimum and
Description
Description
J
J
= 135°C, VCC = 1.425 V
= 115°C, V
R e visio n 1
CC
= 1.425 V
2-80.
Table 2-5 on page 2-5
Table 2-5 on page 2-5
Table 2-114 on page 2-79
Min.
Min.
0.87
0.86
0.85
0.84
1
1
–1
–1
Max.
Max.
1.16
1.20
0.35
1.13
1.18
0.34
for derating values.
for derating values.
2
2
Min.
Min.
1.02
1.01
1.00
0.99
1
1
Std.
Std.
to
Table 2-125 on
Max.
Max.
1.37
1.42
0.41
1.33
1.38
0.40
2
2
Units
Units
MHz
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns