A3P125-QNG132 MICROSEMI, A3P125-QNG132 Datasheet - Page 22

• Manufacturer Part Number: A3P125-QNG132
• Manufacturer: MICROSEMI

Specifications of A3P125-QNG132

• Lead Free Status / Rohs Status: Compliant

Automotive ProASIC3 DC and Switching Characteristics
2- 10
Total Static Power Consumption—P
N
N
Total Dynamic Power Consumption—P
Global Clock Contribution—P
N
page
N
page
F
N
P
Sequential Cells Contribution—P
N
sequential cell is used, it should be accounted for as 1.
α
F
Combinatorial Cells Contribution—P
N
α
F
Routing Net Contribution—P
N
N
α
F
I/O Input Buffer Contribution—P
N
α
F
CLK
AC1
CLK
CLK
CLK
CLK
INPUTS
OUTPUTS
SPINE
ROW
S-CELL
S-CELL
C-CELL
S-CELL
C-CELL
INPUTS
1
1
1
2
is the toggle rate of VersaTile outputs—guidelines are provided in
is the toggle rate of VersaTile outputs—guidelines are provided in
is the toggle rate of VersaTile outputs—guidelines are provided in
is the I/O buffer toggle rate—guidelines are provided in
P
P
P
P
P
P
P
, P
STAT
DYN
CLOCK
S-CELL
C-CELL
NET
INPUTS
2-11.
2-11.
is the global clock signal frequency.
is the global clock signal frequency.
is the global clock signal frequency.
is the global clock signal frequency.
is the global clock signal frequency.
is the number of VersaTile rows used in the design—guidelines are provided in
AC2
is the number of global spines used in the user design—guidelines are provided in
is the number of VersaTiles used as sequential modules in the design.
is the number VersaTiles used as sequential modules in the design.
is the number of VersaTiles used as combinatorial modules in the design.
is the number of VersaTiles used as combinatorial modules in the design.
is the number of I/O input buffers used in the design.
is the number of I/O input buffers used in the design.
is the number of VersaTiles used as sequential modules in the design. When a multi-tile
= (N
= P
= P
is the number of I/O output buffers used in the design.
, P
= (P
= N
= N
= N
CLOCK
DC1
AC3
S-CELL
S-CELL
C-CELL
AC1
INPUTS
, and P
+ N
+ P
+ N
+ N
INPUTS
*
* (P
S-CELL
*
SPINE
α
AC4
C-CELL
α
1
AC5
2
/ 2 * P
/ 2 * P
are device-dependent.
* P
*P
+ P
+
) *
DC2
AC2
α
AC7
α
C-CELL
1
NET
AC9
CLOCK
1
+ N
+ N
/ 2 * P
/ 2 * P
* F
INPUTS
* F
ROW
OUTPUTS
S-CELL
CLK
+ P
CLK
AC6
STAT
AC8
C-CELL
NET
* P
R e visio n 1
) * F
DYN
AC3
* F
* P
+ P
CLK
CLK
+ N
DC3
INPUTS
S-CELL
Table 2-12 on page
+ P
* P
OUTPUTS
AC4
) * F
Table 2-12 on page
Table 2-12 on page
Table 2-12 on page
+ P
CLK
MEMORY
2-11.
+ P
PLL
2-11.
2-11.
2-11.
Table 2-12 on
Table 2-12 on