RC28F320J3F75A Micron Technology Inc, RC28F320J3F75A Datasheet - Page 37

• Manufacturer Part Number: RC28F320J3F75A
• Manufacturer: Micron Technology Inc

Specifications of RC28F320J3F75A

• Lead Free Status / Rohs Status: Supplier Unconfirmed

Numonyx
Note:
9.3.2
Note:
Note:
Note:
Jan 2011
208032-03
®
Embedded Flash Memory (J3 65 nm) Single Bit per Cell (SBC)
During programming, STS and the Status Register indicate a busy status (SR.7 = 0).
Upon completion, STS and the Status Register indicate a ready status (SR.7 = 1). The
Status Register should be checked for any errors (SR.4), then cleared.
Issuing the Read Array command to the device while it is actively programming causes
subsequent reads from the device to output invalid data. Valid array data is output only
after the program operation has finished.
Standby power levels are not be realized until the programming operation has finished.
Also, asserting RP# aborts the programming operation, and array contents at the
addressed location are indeterminate. The addressed block should be erased, and the
data re-programmed. If a Single-Word/Byte program is attempted when the
corresponding block lock-bit is set, SR.1 and SR.4 will be set.
Buffered Programming
Buffered programming operations simultaneously program multiple words/bytes into
the flash memory array, significantly reducing effective word-write/byte-write times.
User-data is first written to a write buffer, then programmed into the flash memory
array in buffer-size increments. For additional details, see the flow chart of the
buffered-programming operation.
Optimal performance and power consumption is realized by aligning the start address
on 256-Word boundaries (i.e., A[8:1] = 00000000b). Crossing a 256-Word boundary
during a buffered programming operation can cause programming time to double.
To perform a buffered programming operation, first issue the Buffered Program setup
command at the desired starting address. The read mode of the device/addressed
partition is automatically changed to Read Status Register mode.
Polling SR.7 determines write-buffer availability (0 = not available, 1 = available). If
the write buffer is not available, re-issue the setup command and check SR.7; repeat
until SR.7 = 1.
The device defaults to output SR data after the Buffered Programming Setup command
(E8h) is issued. CE# and OE# must be toggled to update Status Register. Don’t issue
the Read SR command (70h), which would be interpreted by the internal state machine
as Buffer Word Count.
Next, issue the word count at the desired starting address. The word count represents
the total number of words to be written into the write buffer, minus one. This value can
range from 00h (one) to a maximum of FFh (256). Exceeding the allowable range
causes an abort.
The maximum number of bytes in write buffer on CFI region (offset 2Ah, refer
“Device Geometry Definition” on page
compatible reasons. No software change is required on existing applications for both x8
and x16 mode. Applications can optimize the system performance using the maximum
of 256 buffer size. Please contact your sales representatives for questions.
Following the word count, the write buffer is filled with user-data. Subsequent bus-
write cycles provide addresses and data, up to the word count. All user-data addresses
must lie between <starting address> and <starting address + word count>, otherwise
the WSM continues to run as normal but, user may advertently change the content in
unexpected address locations.
User-data is programmed into the flash array at the address issued when filling the
write buffer.
60) is set to 05h (32 bytes) for backward
Table 41,
Datasheet
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