RC28F320J3F75A Micron Technology Inc, RC28F320J3F75A Datasheet - Page 26

• Manufacturer Part Number: RC28F320J3F75A
• Manufacturer: Micron Technology Inc

Specifications of RC28F320J3F75A

• Lead Free Status / Rohs Status: Supplier Unconfirmed

Table 12: Write Operations
Datasheet
26
Notes:
1.
2.
3.
4.
5.
6.
7.
8.
9.
10.
W11
W12
W13
W15
W1
W2
W3
W4
W5
W6
W7
W8
W9
#
CE
combination of pins CE0, CE1, and CE2 that disable the device (see
32-, 64-, 128-Mb” on page 30
Read timing characteristics during block erase, program, and lock-bit configuration operations are the same as during
read-only operations. Refer to AC Characteristics–Read-Only Operations.
A write operation can be initiated and terminated with either CE
Sampled, not 100% tested.
Write pulse width (t
(whichever goes high first). Hence, t
Refer to
program, or lock-bit configuration.
Write pulse width high (t
low (whichever goes low first). Hence, t
For array access, t
STS timings are based on STS configured in its RY/BY# default mode.
V
= 0).
t
t
t
t
t
t
t
t
t
t
WHEH
DVWH
WHDX
AVWH
WHAX
VPWH
WHGL
WHRL
PEN
PHWL
ELWL
X
Symbol
t
low is defined as the combination of pins CE0, CE1, and CE2 that enable the device. CE
t
should be held at V
t
QVVL
WPH
WP
(t
(t
(t
(t
(t
(t
(t
(t
(t
(t
WLEL
EHWH
PHEL
DVEH
AVEH
EHDX
EHAX
VPEH
EHGL
EHRL
Table 18, “Enhanced Configuration Register” on page 32
)
)
)
)
)
)
)
)
)
)
RP# High Recovery to WE# (CE
CE
Write Pulse Width
Data Setup to WE# (CE
Address Setup to WE# (CE
CE
Data Hold from WE# (CE
Address Hold from WE# (CE
Write Pulse Width High
V
Write Recovery before Read
WE# (CE
V
PEN
PEN
AVQV
X
X
WP
(WE#) Low to WE# (CE
(WE#) Hold from WE# (CE
Setup to WE# (CE
Hold from Valid SRD, STS Going High
) is defined from CE
is required in addition to t
PENH
WPH
X
) High to STS Going Low
) is defined from CE
until determination of block erase, program, or lock-bit configuration success (SR[5:3,1]
Parameter
WP
).
Numonyx
WPH
= t
X
X
) Going High
) Going High
X
X
WLWH
) High
X
or WE# going low (whichever goes low last) to CE
= t
) Going High
X
X
) Going Low
) High
WHWL
X
X
X
= t
) High
WHGL
) Going Low
or WE# going high (whichever goes high first) to CE
®
ELEH
Embedded Flash Memory (J3 65 nm) Single Bit per Cell (SBC)
= t
for any accesses after a write.
EHEL
= t
WLEH
= t
X
WHEL
128 Mbit
= t
Density
32 Mbit
64 Mbit
or WE#.
All
ELWH
Table 17, “Chip Enable Truth Table for
= t
EHWL
.
.
Min
150
180
210
60
50
55
30
35
—
Valid for All
0
0
0
0
0
0
for valid A
Speeds
Max
500
—
—
—
—
—
—
—
—
—
—
—
—
—
—
IN
X
high is defined as the
X
and D
or WE# going high
Unit
IN
ns
X
for block erase,
or WE# going
1,2,3,4,
1,2,3,4
1,2,3,5
1,2,3,5
1,2,3,6
1,2,3,6
1,2,3,7
1,2,3,4
1,2,3,8
1,2,3,9
208032-03
Notes
1,2,3
1,2,3
1,2,3
9,10
Jan 2011