DS2152L+ Maxim Integrated Products, DS2152L+ Datasheet - Page 76

• Manufacturer Part Number: DS2152L+
• Description: IC TXRX T1 1CHIP ENHNCD 100-LQFP
• Manufacturer: Maxim Integrated Products

Specifications of DS2152L+

• Function: Single-Chip Transceiver
• Interface: T1
• Number Of Circuits: 1
• Voltage - Supply: 4.75 V ~ 5.25 V
• Current - Supply: 75mA
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: *
• Includes: DSX-1 and CSU Line Build-Out Generator, HDLC Controller, In-Band Loop Code Generator and Detector
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Power (watts): -

15.1 Receive Clock and Data Recovery
The DS2152 contains a digital clock recovery system. See
The DS2152 couples to the receive T1 twisted pair via a 1:1 transformer. See
details. The 1.544MHz clock attached at the MCLK pin is internally multiplied by 16 via an internal PLL
and fed to the clock recovery system. The clock recovery system uses the clock from the PLL circuit to
form a 16 times oversampler which is used to recover the clock and data. This oversampling technique
offers outstanding jitter tolerance (see
Normally, the clock that is output at the RCLKO pin is the recovered clock from the T1 AMI/B8ZS
waveform presented at the RTIP and RRING inputs. When no AMI signal is present at RTIP and RRING,
a Receive Carrier Loss (LRCL) condition will occur and the RCLKO will be sourced from the clock
applied at the MCLK pin. If the jitter attenuator is either placed in the transmit path or is disabled, the
RCLKO output can exhibit slightly shorter high cycles of the clock. This is due to the highly over-
sampled digital clock recovery circuitry. If the jitter attenuator is placed in the receive path (as is the case
in most applications), the jitter attenuator restores the RCLK to being close to 50% duty cycle. See the
Receive AC Timing Characteristics in Section
15.2 Transmit Waveshaping and Line Driving
The DS2152 uses a set of laser-trimmed delay lines along with a precision Digital-to-Analog Converter
(DAC) to create the waveforms that are transmitted onto the T1 line. The waveforms created by the
DS2152 meet the latest ANSI, AT&T, and ITU specifications. See
which waveform is to be generated by properly programming the L2/L1/L0 bits in the Line Interface
Control Register (LICR). The DS2152 can set up in a number of various configurations depending on the
application. See
Table 15-1. Line Build-Out Select in LICR
Due to the nature of the design of the transmitter in the DS2152, very little jitter (less than 0.005UI
broadband from 10Hz to 100kHz) is added to the jitter present on TCLKI. Also, the waveforms that they
create are independent of the duty cycle of TCLK. The transmitter in the DS2152 couples to the T1
transmit twisted pair via a 1:1.15 or 1:1.36 step-up transformer as shown in
to create the proper waveforms, this transformer used must meet the specifications listed in
L2
0
0
0
0
1
1
1
1
L1
0
0
1
1
0
1
1
0
Table 15-1
L0
0
1
0
1
0
1
0
1
LINE BUILD-OUT
0 to 133ft/0dB
133ft to 266ft
266ft to 399ft
399ft to 533ft
533ft to 655ft
and
-22.5dB
-7.5dB
-15dB
Figure
Figure
15-1.
15-2).
18
APPLICATION
76 of 97
for more details.
DSX-1/CSU
DSX-1
DSX-1
DSX-1
DSX-1
CSU
CSU
CSU
Figure 1-1
Figure
and
Figure 15-1
Figure
Table 15-2
15-3. The user will select
15-1. For the devices
for more details.
for transformer
Table
15-2.
P-P