DS2152L+ Maxim Integrated Products, DS2152L+ Datasheet - Page 12

• Manufacturer Part Number: DS2152L+
• Description: IC TXRX T1 1CHIP ENHNCD 100-LQFP
• Manufacturer: Maxim Integrated Products

Specifications of DS2152L+

• Function: Single-Chip Transceiver
• Interface: T1
• Number Of Circuits: 1
• Voltage - Supply: 4.75 V ~ 5.25 V
• Current - Supply: 75mA
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: *
• Includes: DSX-1 and CSU Line Build-Out Generator, HDLC Controller, In-Band Loop Code Generator and Detector
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Power (watts): -

2.2 Receive Side Digital Pins
PIN
PIN
100
39
40
78
79
82
92
95
98
97
96
85
94
1
RSYSCLK
RMSYNC
RCHCLK
RCHBLK
RFSYNC
RDATA
TNEGI
RSYNC
TCLKI
NAME
RLCLK
NAME
RLINK
RCLK
RSER
RSIG
transmitted out onto the T1 line. Can be internally connected to TPOSO by tying the
LIUC pin high. TPOSI and TNEGI can be tied together in NRZ applications.
Transmit Negative Data Input. Sampled on the falling edge of TCLKI for data to be
transmitted out onto the T1 line. Can be internally connected to TNEGO by tying the
LIUC pin high. TPOSI and TNEGI can be tied together in NRZ applications.
Transmit Clock Input. Line interface transmit clock. Can be internally connected to
TCLKO by tying the LIUC pin high.
Receive Clock. 1.544MHz clock that is used to clock data through the receive side
framer.
Receive Channel Clock. A 192kHz clock that pulses high during the LSB of each
channel. Synchronous with RCLK when the receive side elastic store is disabled.
Synchronous with RSYSCLK when the receive side elastic store is enabled. Useful for
parallel to serial conversion of channel data.
Receive Channel Block. A user-programmable output that can be forced high or low
during any of the 24 T1 channels. Synchronous with RCLK when the receive side elastic
store is disabled. Synchronous with RSYSCLK when the receive side elastic store is
enabled. Useful for blocking clocks to a serial UART or LAPD controller in applications
where not all T1 channels are used, such as Fractional T1, 384kbps service, 768kbps, or
ISDN-PRI. Also useful for locating individual channels in drop-and-insert applications,
for external per-channel loopback, and for per-channel conditioning. See Section
details.
Receive Serial Data. Received NRZ serial data. Updated on rising edges of RCLK
when the receive side elastic store is disabled. Updated on the rising edges of
RSYSCLK when the receive side elastic store is enabled.
Receive Sync. An extracted pulse, one RCLK wide, is output at this pin, which
identifies either frame (RCR2.4 = 0) or multiframe (RCR2.4 = 1) boundaries. If set to
output frame boundaries then via RCR2.5, RSYNC can also be set to output double-
wide pulses on signaling frames. If the receive side elastic store is enabled via CCR1.2,
then this pin can be enabled to be an input via RCR2.3 at which a frame or multiframe
boundary pulse is applied. See Section
Receive Frame Sync. An extracted 8kHz pulse 1 RCLK wide is output at this pin that
identifies frame boundaries.
Receive Multiframe Sync. Only used when the receive side elastic store is enabled. An
extracted pulse, 1 RSYSCLK wide, is output at this pin, which identifies multiframe
boundaries. If the receive side elastic store is disabled, then this output will output
multiframe boundaries associated with RCLK.
Receive Data. Updated on the rising edge of RCLK with the data out of the receive side
framer.
Receive System Clock. 1.544MHz or 2.048MHz clock. Only used when the elastic
store function is enabled. Should be tied low in applications that do not use the elastic
store. Can be burst at rates up to 8.192MHz.
Receive Signaling Output. Outputs signaling bits in a PCM format. Updated on rising
edges of RCLK when the receive side elastic store is disabled. Updated on the rising
edges of RSYSCLK when the receive side elastic store is enabled.
Receive Link Data. Updated with either FDL data (ESF) or Fs bits (D4) or Z bits
(ZBTSI) one RCLK before the start of a frame. See Section
Receive Link Clock. A 4kHz or 2 kHz (ZBTSI) clock for the RLINK output.
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FUNCTION
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