DS2152L+ Maxim Integrated Products, DS2152L+ Datasheet - Page 13

• Manufacturer Part Number: DS2152L+
• Description: IC TXRX T1 1CHIP ENHNCD 100-LQFP
• Manufacturer: Maxim Integrated Products

Specifications of DS2152L+

• Function: Single-Chip Transceiver
• Interface: T1
• Number Of Circuits: 1
• Voltage - Supply: 4.75 V ~ 5.25 V
• Current - Supply: 75mA
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: *
• Includes: DSX-1 and CSU Line Build-Out Generator, HDLC Controller, In-Band Loop Code Generator and Detector
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Power (watts): -

2.3 Parallel Control Port Pins
56–65
66–72
PIN
PIN
99
93
91
90
89
86
87
88
25
14
55
11
74
75
73
77
6
3
RLOS/LOTC
AD0–AD7
WR(R/W)
ALE(AS)
RD(DS)
D0–D7/
8MCLK
RNEGO
RCLKO
RPOSO
A0–A6
NAME
RNEGI
RCLKI
NAME
RSIGF
RPOSI
MUX
TEST
BTS
RCL
INT
CS
Bus Operation. Set low to select nonmultiplexed bus operation. Set high to select
multiplexed bus operation.
Data Bus or Address/Data Bus. In nonmultiplexed bus operation (MUX = 0), serves as
the data bus. In multiplexed bus operation (MUX = 1), serves as an 8-bit multiplexed
address/data bus.
Address Bus. In nonmultiplexed bus operation (MUX = 0), serves as the address bus. In
multiplexed bus operation (MUX = 1), these pins are not used and should be tied low.
Bus Type Select. Strap high to select Motorola bus timing; strap low to select Intel bus
timing. This pin controls the function of the
If BTS = 1, then these pins assume the function listed in parentheses.
Read Input (Data Strobe).
active high when MUX = 0. See bus timing diagrams.
Chip Select. Must be low to read or write to the device.
A7 or Address Latch Enable (Address Strobe). In non-multiplexed bus operation
(MUX = 0), serves as the upper address bit. In multiplexed bus operation (MUX = 1),
serves to demultiplex the bus on a positive-going edge.
Write Input (Read/Write).
Interrupt. Flags host controller during conditions and change of conditions defined in
the Status Registers 1 and 2 and the FDL Status Register. Active-low, open-drain
output.
Tri-State Control. Set high to tri-state all output and I/O pins (including the parallel
control port). Set low for normal operation. Useful in board-level testing.
Receive Loss of Sync/Loss of Transmit Clock. A dual function output that is
controlled by the CCR3.5 control bit. This pin can be programmed to either toggle high
when the synchronizer is searching for the frame and multiframe or to toggle high if the
TCLK pin has not been toggled for 5µs.
Receive Carrier Loss. Set high when the line interface detects a loss of carrier.
Receive Signaling Freeze. Set high when the signaling data is frozen via either
automatic or manual intervention. Used to alert downstream equipment of the condition.
8MHz Clock. A 8.192MHz output clock that is referenced to the clock that is output at
the RCLK pin and is used to clock data through the receive side framer.
Receive Positive Data Output. Updated on the rising edge of RCLKO with the bipolar
data out of the line interface. This pin is normally tied to RPOSI.
Receive Negative Data Output. Updated on the rising edge of RCLKO with the bipolar
data out of the line interface. This pin is normally tied to RNEGI.
Receive Clock Output. Buffered recovered clock from the T1 line. This pin is normally
tied to RCLKI.
Receive Positive Data Input. Sampled on the falling edge of RCLKI for data to be
clocked through the receive side framer. RPOSI and RNEGI can be tied together for a
NRZ interface. Can be internally connected to RPOSO by tying the LIUC pin high.
Receive Negative Data Input. Sampled on the falling edge of RCLKI for data to be
clocked through the receive side framer. RPOSI and RNEGI can be tied together for a
NRZ interface. Can be internally connected to RNEGO by tying the LIUC pin high.
Receive Clock Input. Clock used to clock data through the receive side framer. This pin
is normally tied to RCLKO. Can be internally connected to RCLKO by tying the LIUC
pin high.
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RD
WR
and
is an active-low signal.
DS
FUNCTION
FUNCTION
are active-low signals when MUX = 1. DS is
RD
(
DS
), ALE(AS), and
CS
is an active-low signal.
WR
(R/
W
) pins.