AT91SAM7X128 Atmel, AT91SAM7X128 Datasheet - Page 490
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AT91SAM7X128
Manufacturer Part Number
AT91SAM7X128
Description
MCU 32-Bit 91S ARM7TDMI RISC 128KB Flash 1.8V/3.3V 100-Pin LQFP
Manufacturer
Atmel
Datasheet
1.AT91SAM7X512-AU-999.pdf
(687 pages)
Specifications of AT91SAM7X128
Package
100LQFP
Device Core
ARM7TDMI
Family Name
91S
Maximum Speed
55 MHz
Ram Size
32 KB
Program Memory Size
128 KB
Operating Supply Voltage
1.8|3.3 V
Data Bus Width
32 Bit
Program Memory Type
Flash
Number Of Programmable I/os
62
Interface Type
CAN/Ethernet/SPI/I2S/TWI/USART/USB
On-chip Adc
8-chx10-bit
Operating Temperature
-40 to 85 °C
Number Of Timers
3
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35.5.6
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AT91SAM7X512/256/128 Preliminary
Conversion Triggers
Sleep Mode and Conversion Sequencer
Conversions of the active analog channels are started with a software or a hardware trigger. The
software trigger is provided by writing the Control Register (ADC_CR) with the bit START at 1.
The hardware trigger can be one of the TIOA outputs of the Timer Counter channels, or the
external trigger input of the ADC (ADTRG). The hardware trigger is selected with the field TRG-
SEL in the Mode Register (ADC_MR). The selected hardware trigger is enabled with the bit
TRGEN in the Mode Register (ADC_MR).
If a hardware trigger is selected, the start of a conversion is triggered after a delay starting at
each rising edge of the selected signal. Due to asynchronism handling, the delay may vary in a
range of 2 MCK clock periods to 1 ADC clock period.
If one of the TIOA outputs is selected, the corresponding Timer Counter channel must be pro-
grammed in Waveform Mode.
Only one start command is necessary to initiate a conversion sequence on all the channels. The
ADC hardware logic automatically performs the conversions on the active channels, then waits
for a new request. The Channel Enable (ADC_CHER) and Channel Disable (ADC_CHDR) Reg-
isters enable the analog channels to be enabled or disabled independently.
If the ADC is used with a PDC, only the transfers of converted data from enabled channels are
performed and the resulting data buffers should be interpreted accordingly.
Warning: Enabling hardware triggers does not disable the software trigger functionality. Thus, if
a hardware trigger is selected, the start of a conversion can be initiated either by the hardware or
the software trigger.
The ADC Sleep Mode maximizes power saving by automatically deactivating the ADC when it is
not being used for conversions. Sleep Mode is selected by setting the bit SLEEP in the Mode
Register ADC_MR.
The SLEEP mode is automatically managed by a conversion sequencer, which can automati-
cally process the conversions of all channels at lowest power consumption.
When a start conversion request occurs, the ADC is automatically activated. As the analog cell
requires a start-up time, the logic waits during this time and starts the conversion on the enabled
channels. When all conversions are complete, the ADC is deactivated until the next trigger. Trig-
gers occurring during the sequence are not taken into account.
The conversion sequencer allows automatic processing with minimum processor intervention
and optimized power consumption. Conversion sequences can be performed periodically using
a Timer/Counter output. The periodic acquisition of several samples can be processed automat-
ically without any intervention of the processor thanks to the PDC.
Note:
The reference voltage pins always remain connected in normal mode as in sleep mode.
trigger
start
delay
6120H–ATARM–17-Feb-09
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