AT91SAM7X128 Atmel, AT91SAM7X128 Datasheet - Page 427
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AT91SAM7X128
Manufacturer Part Number
AT91SAM7X128
Description
MCU 32-Bit 91S ARM7TDMI RISC 128KB Flash 1.8V/3.3V 100-Pin LQFP
Manufacturer
Atmel
Datasheet
1.AT91SAM7X512-AU-999.pdf
(687 pages)
Specifications of AT91SAM7X128
Package
100LQFP
Device Core
ARM7TDMI
Family Name
91S
Maximum Speed
55 MHz
Ram Size
32 KB
Program Memory Size
128 KB
Operating Supply Voltage
1.8|3.3 V
Data Bus Width
32 Bit
Program Memory Type
Flash
Number Of Programmable I/os
62
Interface Type
CAN/Ethernet/SPI/I2S/TWI/USART/USB
On-chip Adc
8-chx10-bit
Operating Temperature
-40 to 85 °C
Number Of Timers
3
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6120H–ATARM–17-Feb-09
Figure 33-4. Non Overlapped Center Aligned Waveforms
Note:
• the waveform duty cycle. This channel parameter is defined in the CDTY field of the
• the waveform polarity. At the beginning of the period, the signal can be at high or low level.
• the waveform alignment. The output waveform can be left or center aligned. Center aligned
By using a Master Clock divided by one of both DIVA or DIVB divider, the formula becomes,
respectively:
If the waveform is center aligned then the output waveform period depends on the counter
source clock and can be calculated:
By using the Master Clock (MCK) divided by an X given prescaler value
(with X being 1, 2, 4, 8, 16, 32, 64, 128, 256, 512, or 1024). The resulting period formula will
be:
By using a Master Clock divided by one of both DIVA or DIVB divider, the formula becomes,
respectively:
PWM_CDTYx register.
If the waveform is left aligned then:
If the waveform is center aligned, then:
This property is defined in the CPOL field of the PWM_CMRx register. By default the signal
starts by a low level.
waveforms can be used to generate non overlapped waveforms. This property is defined in
the CALG field of the PWM_CMRx register. The default mode is left aligned.
(
------------------------------------------ -
(
------------------------------------------ -
(
----------------------------------------------------- -
PWM0
PWM1
CRPD
2
2
duty cycle
duty cycle
×
×
X
CPRD
See
MCK
MCK
×
MCK
×
CPRD
Figure 33-5 on page 429
DIVA
×
=
DIVA
=
No overlap
)
)
(
----------------------------------------------------------------------------------------------------------- -
(
----------------------------------------------------------------------------------------------------------------------------- -
period 1
or
(
period
)
(
---------------------------------------------- -
or
CRPD
AT91SAM7X512/256/128 Preliminary
Period
(
----------------------------------------------------- -
–
2
⁄
MCK
×
×
2
⁄
CPRD
) 1
DIVAB
fchannel_x_clock
–
MCK
for a detailed description of center aligned waveforms.
period
⁄
(
×
period
)
fchannel_x_clock
DIVB
)
⁄
2
)
×
CDTY
×
CDTY
)
) )
427
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