NAND512R3A2SZA6E Micron Technology Inc, NAND512R3A2SZA6E Datasheet - Page 13

• Manufacturer Part Number: NAND512R3A2SZA6E
• Manufacturer: Micron Technology Inc

Specifications of NAND512R3A2SZA6E

• Cell Type: NAND
• Density: 512Mb
• Access Time (max): 15us
• Interface Type: Parallel
• Boot Type: Not Required
• Address Bus: 26b
• Operating Supply Voltage (typ): 1.8V
• Operating Temp Range: -40C to 85C
• Package Type: VFBGA
• Sync/async: Asynchronous
• Operating Temperature Classification: Industrial
• Operating Supply Voltage (min): 1.7V
• Operating Supply Voltage (max): 1.95V
• Word Size: 8b
• Number Of Words: 64M
• Supply Current: 15mA
• Mounting: Surface Mount
• Pin Count: 63
• Lead Free Status / Rohs Status: Supplier Unconfirmed

Numonyx SLC SP 70 nm
3
Signal descriptions
See
connected to the devices.
Table 5.
Input/Output signals
I/O0-I/O7
I/O8-I/O15
Control signals
AL
CL
E
Figure 1: Logic
Symbol
Signal descriptions
Input/Output
Input/Output
Input
Input
Input
diagram, and
Type
Table 5
210403 - Rev 3
Table 3: Signal
provides the detailed descriptions of the signals.
Input/outputs 0 to 7 are used to input the selected address,
output the data during a read operation or input a
command or data during a write operation. The inputs are
latched on the rising edge of Write Enable. I/O0-I/O7 are
left floating when the device is deselected or the outputs
are disabled.
Input/outputs 8 to 15 are only available in x16 devices.
They are used to output the data during a read operation or
input data during a write operation. Command and address
inputs only require I/O0 to I/O7.
The inputs are latched on the rising edge of Write Enable.
I/O8-I/O15 are left floating when the device is deselected
or the outputs are disabled.
The Address Latch Enable activates the latching of the
address inputs in the command interface. When AL is
High, the inputs are latched on the rising edge of Write
Enable.
The Command Latch Enable activates the latching of the
command inputs in the command interface. When CL is
High, the inputs are latched on the rising edge of Write
Enable.
The Chip Enable input activates the memory control logic,
input buffers, decoders and read circuitry. When Chip
Enable is Low, V
If Chip Enable goes High (V
programming or erasing, the device remains selected and
does not go into standby mode.
While the device is busy reading:
– the Chip Enable input should be held Low during the
– for devices that feature the Chip Enable don’t care
whole busy time (t
the Chip Enable don’t care option. Otherwise, the read
operation in progress is interrupted and the device goes
into standby mode.
option, the Chip Enable going High during the busy time
(t
device will not go into standby mode.
BLBH1
) will not interrupt the read operation and the
names, for a brief overview of the signals
IL
, the device is selected.
BLBH1
Description
) for devices that do not feature
IH
) while the device is busy
Signal descriptions
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