STA2065N STMicroelectronics, STA2065N Datasheet - Page 6

• Manufacturer Part Number: STA2065N
• Description: IC APPL PROCESSOR 472TFBGA
• Manufacturer: STMicroelectronics
• Series: -r

Specifications of STA2065N

• Applications: GPS
• Core Processor: ARM11
• Program Memory Type: -
• Controller Series: Cartesio™
• Ram Size: 8K x 32
• Interface: AC97, CAN, I²C, MSP, MMC/SD, SPDIF, SSP, UART, USB
• Number Of I /o: 160
• Voltage - Supply: 1.8 V ~ 3.3 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: *
• Package / Case: *
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 497-11637

System description
2.3.6
2.3.7
2.3.8
2.3.9
2.3.10
2.4
2.4.1
6/20
Real-time clock (RTC)
The RTC provides a one second resolution clock. This keeps time when the system is
inactive and can be used to wake the system up when a programmed ‘alarm’ time is
reached. It has a clock trimming feature to compensate the drift of the 32.768 kHz crystal.
Real-time timer (RTT)
The RTT has the possibility of being clocked off. This reduces the always_on domain
consumption during Deep Sleep. By default the RTT has its clock enabled.
Always_ON supply
The “Always_ON” domain retains its two separate supplies, one for the core logic (V
and one for the IOs (V
The V
lowest consumption possible, can also be configured as low as 1.0 ±10%V when the device
is in deep-sleep.
Enhanced function timer (EFT)
STA2065 features 4 16-bit EFTs. Each of the four EFT timers has a 16-bit free-running
counter with 7-bit prescaler, up to two input capture/output compare functions, a pulse
counter function, and a PWM channel with selectable frequency.
Watchdog timer (WDT)
This OS resource is used to trigger a system reset in the event of software failure.
Memory interfaces
Flexible static memory controller (FSMC)
The flexible static memory controller (FSMC) supports, with two chip selects:
●
●
●
●
It also supports, with two additional separate chip selects:
●
●
For NAND type of memories, the FSMC has been enhanced to implement an error
correction in hardware, based on the Bose-Chaudhuri-Hocquenghem (BCH) code, able to
correct up to 8-bit over 512 bytes+syndrome. The BCH code will calculate, in hardware, the
syndrome only. The actual correction will be implemented through S/W intervention.
ROM
Static RAM
NOR type flash memories, not multiplexed
NOR type flash memories, multiplexed
NAND type flash memories, SLC small or large page
NAND type flash memories, MLC
DDON
supply is equal to V
IOON
).
Doc ID16050 Rev 3
DD
during normal operation but, with the goal of reaching the
STA2065
DDON
)