STA2065N STMicroelectronics, STA2065N Datasheet - Page 14

• Manufacturer Part Number: STA2065N
• Description: IC APPL PROCESSOR 472TFBGA
• Manufacturer: STMicroelectronics
• Series: -r

Specifications of STA2065N

• Applications: GPS
• Core Processor: ARM11
• Program Memory Type: -
• Controller Series: Cartesio™
• Ram Size: 8K x 32
• Interface: AC97, CAN, I²C, MSP, MMC/SD, SPDIF, SSP, UART, USB
• Number Of I /o: 160
• Voltage - Supply: 1.8 V ~ 3.3 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: *
• Package / Case: *
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 497-11637

System features introduction
3.3
14/20
Frequency and power range
The core voltage range is 1.25 ±4 %V while the IO voltage ranges are 1.8 ±10 %V,
2.5 ± 10 %V and 3.3 ± 10 %V.
Table 2
Table 2.
The background of
matching the currently available DRAM speed grades: 133 MHz, 166 MHz and 200 MHz (LP
DDR) and 333 MHz (DDR2). Despite this, it is possible to program the ARM core, the
internal bus and the DDR to run at different speeds than the ones mentioned in
ARM bus clock and the bus clock are derived from the same common source (VCO of the
PLL1) but are asynchronous each other. The DDR frequency can be the same
(synchronous) or derived with a different prescaling (1,2,3,4,5,6,8,9 or 10) from the VCO of
PLL1 or PLL2 (asynchronous configuration).
STA2065 embeds a complete GPS subsystem where both gate logic and dedicated DSP
work together. There are specific constraints in this subsystem in terms of minimum
frequency in order to guarantee the target GPS specifications.
In the lowest power consumption state as possible, only V
current drawn is 20 μA. In this state, the clock is not running and the current leakage is
mainly due to the Backup memory. The 20 μA current limit has to be considered with
Process best (leakage worst case condition), V
Junction Temperature 50
equal to the junction temperature).
V
dd
and V
1.2 5(±4%)
1.2 5(±4%)
1.2 5(±4%)
1.2 5(±4%)
1.2 5(±4%)
1.2 5(±4%)
1.2 5(±4%)
1.2 5(±4%)
1.2 5(±4%)
1.2 5(±4%)
1.2 5(±4%)
1.2 5(±4%)
1.2 5(±4%)
1.2 5(±4%)
shows some power use cases of STA2065 in NORMAL mode:
dd_on
Frequency and power use cases
(V)
Table 2
o
C (considering, while in this state, the ambient temperature is
Core Freq
is the maximization of data throughput on the DRAM interface,
[MHz]
624
624
624
533
533
533
520
520
520
520
494
494
494
494
Doc ID16050 Rev 3
Bus Freq
177.67
133.25
177.67
173.34
164.67
[MHz]
124.8
197.6
123.5
208
156
208
130
208
208
dd_on
1.3V (1.25V plus 4% tolerance) and
dd_on
DDR Freq
177.67
133.25
173.34
164.67
329.34
[MHz]
124.8
197.6
123.5
is powered and the target
312
156
312
130
130
312
Sync/Async
A, DDR2
A, DDR2
A, DDR2
A, DDR2
Table 2
[S/A]
S
S
S
S
A
S
S
S
S
S
STA2065
The