HD6473837FV Renesas Electronics America, HD6473837FV Datasheet - Page 113

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HD6473837FV

Manufacturer Part Number
HD6473837FV
Description
IC H8/3837 MCU FLASH 100QFP
Manufacturer
Renesas Electronics America
Series
H8® H8/300Lr
Datasheet

Specifications of HD6473837FV

Core Processor
H8/300L
Core Size
8-Bit
Speed
5MHz
Connectivity
SCI
Peripherals
LCD, PWM
Number Of I /o
84
Program Memory Size
60KB (60K x 8)
Program Memory Type
OTP
Eeprom Size
-
Ram Size
2K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 12x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
100-BQFP
Lead Free Status / Rohs Status
Lead free / RoHS Compliant

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5.1.1
The operation mode is selected using the system control registers described in table 5.3.
Table 5.3
Name
System control register 1
System control register 2
System Control Register 1 (SYSCR1)
SYSCR1 is an 8-bit read/write register for control of the power-down modes.
Bit 7—Software Standby (SSBY): This bit designates transition to standby mode or watch mode.
Bit 7: SSBY
0
1
Bits 6 to 4—Standby Timer Select 2 to 0 (STS2 to STS0): These bits designate the time the
CPU and peripheral modules wait for stable clock operation after exiting from standby mode or
watch mode to active mode due to an interrupt. The designation should be made according to the
clock frequency so that the waiting time is at least 10 ms.
96
Bit
Initial value
Read/Write
System Control Registers
System Control Register
SSBY
R/W
Description
7
0
When a SLEEP instruction is executed in active mode, a transition is made
to sleep mode
When a SLEEP instruction is executed in subactive mode, a transition is
made to subsleep mode.
When a SLEEP instruction is executed in active mode, a transition is made
to standby mode or watch mode.
When a SLEEP instruction is executed in subactive mode, a transition is
made to watch mode.
STS2
R/W
Abbreviation
SYSCR1
SYSCR2
6
0
STS1
R/W
5
0
STS0
R/W
4
0
R/W
R/W
R/W
LSON
R/W
3
0
Initial Value
H'07
H'E0
2
1
Address
H'FFF0
H'FFF1
1
1
(initial value)
0
1

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