HD6473837FV Renesas Electronics America, HD6473837FV Datasheet - Page 305
HD6473837FV
Manufacturer Part Number
HD6473837FV
Description
IC H8/3837 MCU FLASH 100QFP
Manufacturer
Renesas Electronics America
Series
H8® H8/300Lr
Datasheet
1.HD6473837HV.pdf
(562 pages)
Specifications of HD6473837FV
Core Processor
H8/300L
Core Size
8-Bit
Speed
5MHz
Connectivity
SCI
Peripherals
LCD, PWM
Number Of I /o
84
Program Memory Size
60KB (60K x 8)
Program Memory Type
OTP
Eeprom Size
-
Ram Size
2K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 12x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
100-BQFP
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
HD6473837FV
Manufacturer:
Renesas Electronics America
Quantity:
10 000
Part Number:
HD6473837FV
Manufacturer:
RENESAS/瑞萨
Quantity:
20 000
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SCI3 operates as follows during data transmission using a multiprocessor format.
SCI3 monitors bit TDRE in SSR. When this bit is cleared to 0, SCI3 recognizes that there is data
written in the transmit data register (TDR), which it transfers to the transmit shift register (TSR).
Then TDRE is set to 1 and transmission starts. If bit TIE in SCR3 is set to 1, a TXI interrupt is
requested.
Serial data is transmitted from pin TXD using the communication format outlined in
table 10.16.
Next, TDRE is checked as the stop bit is being transmitted. If TDRE is 0, data is transferred from
TDR to TSR, and after the stop bit is sent, transmission of the next frame starts. If TDRE is 1, the
TEND bit in SSR is set to 1, and after the stop bit is sent the output remains at 1 (mark state). A
TEI interrupt is requested in this state if bit TEIE in SCR3 is set to 1.
Figure 10.24 shows a typical SCI3 operation in multiprocessor communication mode.
288
Serial
data
TDRE
TEND
SCI3
operation
User
processing
1
TXI request
Start
bit
Figure 10.24 Typical Multiprocessor Format Transmit Operation
0
(8-Bit Data, Multiprocessor Bit Added, and 1 Stop Bit)
D0
TDRE cleared
to 0
Write data in
TDR
D1
Transmit
data
1 frame
D7
MPB
0/1
TXI
request
Stop
bit
1
Start
bit
0
D0
D1
Transmit
data
1 frame
D7
MPB
0/1
TEI
request
Stop
bit
1
Mark
state
1
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