HD6473837FV Renesas Electronics America, HD6473837FV Datasheet - Page 247
HD6473837FV
Manufacturer Part Number
HD6473837FV
Description
IC H8/3837 MCU FLASH 100QFP
Manufacturer
Renesas Electronics America
Series
H8® H8/300Lr
Datasheet
1.HD6473837HV.pdf
(562 pages)
Specifications of HD6473837FV
Core Processor
H8/300L
Core Size
8-Bit
Speed
5MHz
Connectivity
SCI
Peripherals
LCD, PWM
Number Of I /o
84
Program Memory Size
60KB (60K x 8)
Program Memory Type
OTP
Eeprom Size
-
Ram Size
2K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 12x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
100-BQFP
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
HD6473837FV
Manufacturer:
Renesas Electronics America
Quantity:
10 000
Part Number:
HD6473837FV
Manufacturer:
RENESAS/瑞萨
Quantity:
20 000
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Bits 4 to 2—Reserved Bits: Bits 4 to 2 are reserved; they are always read as 0, and cannot be
modified.
Bit 1—Reserved Bit: Bit 1 is reserved; it should always be cleared to 0.
Bit 0—Start Flag (STF): Bit 0 controls the start of a transfer. Setting this bit to 1 causes SCI1 to
start transferring data.
During the transfer or while waiting for the first clock pulse, this bit remains set to 1. It is cleared
to 0 upon completion of the transfer. It can therefore be used as a busy flag.
Bit 0: STF
0
1
Serial Data Register U (SDRU)
SDRU is an 8-bit read/write register. It is used as the data register for the upper 8 bits in 16-bit
transfer (SDRL is used for the lower 8 bits).
Data written to SDRU is output to SDRL starting from the least significant bit (LSB). This data is
then replaced by LSB-first data input at pin SI
significant bit (MSB) toward the LSB.
SDRU must be written or read only after data transmission or reception is complete. If this register
is written or read while a data transfer is in progress, the data contents are not guaranteed.
The SDRU value upon reset is not fixed.
230
Bit
Initial value
Read/Write
Not fixed Not fixed Not fixed Not fixed Not fixed Not fixed Not fixed Not fixed
SDRU7
Description
Read: Indicates that transfer is stopped
Write: Invalid
Read: Indicates transfer in progress
Write: Starts a transfer operation
R/W
7
SDRU6
R/W
6
SDRU5
R/W
5
1
, which is shifted in the direction from the most
SDRU4
R/W
4
SDRU3
R/W
3
SDRU2
R/W
2
SDRU1
R/W
1
(initial value)
SDRU0
R/W
0
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